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Si53340-B-GM

Description
clock drivers & distribution lvds buffer inpt mux footprint compatible
Categorylogic    logic   
File Size967KB,38 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
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Si53340-B-GM Overview

clock drivers & distribution lvds buffer inpt mux footprint compatible

Si53340-B-GM Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Parts packaging codeQFN
package instructionHVQCCN, LCC16,.12SQ,20
Contacts16
Reach Compliance Codecompli
Other featuresALSO OPERATES AT 2.5 V AND 3.3 V SUPPLY
series53340
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-XQCC-N16
JESD-609 codee3
length3 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level2
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC16,.12SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply1.8/3.3 V
Prop。Delay @ Nom-Su1000 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.05 ns
Maximum seat height0.9 mm
Maximum supply voltage (Vsup)1.89 V
Minimum supply voltage (Vsup)1.71 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width3 mm
Si53340-45 Data Sheet
Low-Jitter LVDS Fanout Clock Buffers with up to 10 LVDS Out-
puts from Any-Format Input and Wide Frequency Range from dc
up to 1250 MHz
The Si53340-45 family of LVDS fanout buffers is ideal for clock/data distribution and re-
dundant clocking applications. These devices feature typical ultra-low jitter of 50 fs and
operate over a wide frequency range from dc to 1250 MHz. Built-in LDOs deliver high
PSRR performance and reduces the need for external components simplifying low jitter
clock distribution in noisy environments.
They are available in multiple configurations and offer a selectable input clock using a
2:1 input mux. Other features include independent output enable and built-in format
translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to
deliver end-to-end clock tree performance.
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 LVDS Outputs
• Any-format Inputs (LVPECL, Low-Power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range: dc to 1250 MHz
• Output Enable option
• Multiple configuration options
• 2:1 Input Mux
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
VDD
Power Supply
Filtering
4
4 Outputs
Si53340/41
VDDOA
OEAb
CLK0*
0
3
3
3 Outputs
Si53342/43
CLK1*
CLK_SEL
1
3 Outputs
OEBb
VDDOB
10
10 Outputs
Si53344/45
*Si53341/43/45 require Single-ended Inputs
silabs.com
| Smart. Connected. Energy-friendly.
Rev. 1.2
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