DATASHEET
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
Description
The ICS341 is a low cost, single-output, field programmable
clock synthesizer. The ICS341 can generate an output
frequency from 250 kHz to 200 MHz and may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
Using IDT’s VersaClock
™
software to configure the PLL and
output, the ICS341 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Programming
features include 4 selectable configuration registers.
The device employs Phase-Locked Loop (PLL) techniques
to run from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
The device also has a power-down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS341 is also available in factory programmed custom
versions for high-volume applications.
ICS341
Features
•
8-pin SOIC package (Pb-free)
•
Highly accurate frequency generation
•
M/N Multiplier PLL: M = 1...2048, N = 1...1024
•
Output clock frequencies up to 200 MHz
•
Four ROM locations for frequency and spread selection
•
Spread spectrum capability for lower system EMI
•
Center or Down Spread up to 4% total
•
Selectable 32 kHz or 120 kHz modulation
•
Input crystal frequency from 5 to 27 MHz
•
Input clock frequency from 2 to 50 MHz
•
Operating voltage of 3.3 V
•
Advanced, low-power CMOS process
•
For two output clocks, use the ICS342. For three output
clocks, see the ICS343. For more than three outputs, see
the ICS345 or ICS348.
Block Diagram
VDD
S1:0
2
OTP ROM
with PLL
Divider
Values
Crystal or
clock input
X1/ICLK
Crystal
Oscillator
X2
External capacitors are
required with a crystal input.
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
CLK
GND
PDTS (output and PLL)
IDT® / ICS™
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
1
ICS341
REV N 072816
ICS341
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Pin Assignment
X1/ I CLK
VDD
GND
S0
1
2
3
4
8
7
6
5
X2
PDTS
S1
CLK
Output Clock Selection Table
S1
0
0
1
1
S0
0
1
0
1
CLK (MHz)
User
Configurable
User
Configurable
User
Configurable
User
Configurable
Spread
Percentage
User
Configurable
User
Configurable
User
Configurable
User
Configurable
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1/ICLK
VDD
GND
S0
CLK
S1
PDTS
X2
Pin
Type
XI
Power
Power
Input
Output
Input
Input
XO
Connect to +3.3 V.
Connect to ground.
Pin Description
Connect this pin to a crystal or external clock input.
Select pin 0 for frequency selection on CLK. Internal pull-up resistor.
Clock output. Weak internal pull-down when tri-state.
Select pin 1 for frequency selection on CLK. Internal pull-up resistor.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up
resistor.
Connect this pin to a crystal, or float for clock input.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20.
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS341
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should be
kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
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ICS341
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Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
IDT® / ICS™
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
ICS341
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
3) To minimize EMI, the 33 series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS341. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
The modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective average
frequency is equal to the target frequency. In applications
where the clock is driving a component with a maximum
frequency rating, down spread should be applied. In this
case, the maximum frequency, including modulation, is the
target frequency. The effective average frequency is less
than the target frequency.
The ICS341 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between +/- 0.125% to +/-2.0%. For down
spread, the frequency can be modulated between -0.25% to
-4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
ICS341 Configuration Capabilities
The architecture of the ICS341 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS341 also provides separate output divide values,
from 2 through 20, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented
as:
OutputFreq
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
=
REFFreq
-------------------------------------
-
OutputDivide
----
-
M
N
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Using VersaClock Products with an Input Clock
Source
In order to ensure proper startup with an input clock rather
than a crystal, the supply voltage must be within the
operating range (3.3V ±10%) and the input signal must be
stable and free from glitching. The input clock must provide
pulses of at least 20ns, and no more than 500ns, for at least
160 clock cycles without any interruptions to the clock or
power during this period. It may take up to 4ms for output
frequencies to reach their target frequency values.
An alternative method is to have the PDTS pin asserted low
while power supplies and clock sources stabilize.Once the
power supply and input clock source are constant and within
the acceptable frequency range, bring PDTS high. This
approach is preferred if the clock source is derived from
another PLL, or the source oscillator produces
unpredictable output pulses prior to stabilization. No
considerations need to be taken when using a crystal input
source with VersaClock products.
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ICS341
REV N 072816
Spread Spectrum Modulation
The ICS341 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electro-magnetic interference (EMI).
IDT® / ICS™
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
ICS341
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS341. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Junction Temperature
Condition
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-0.5
-65
Typ.
Max.
7
VDD+ 0.5
VDD+ 0.5
150
260
125
Units
V
V
V
C
C
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS341M)
Ambient Operating Temperature (ICS341MI)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Min.
0
-40
+3.15
Typ.
Max.
+70
+85
Units
C
C
V
ms
+3.3
+3.45
4
IDT® / ICS™
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
4
ICS341
REV N 072816
ICS341
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3V ±5%,
Ambient Temperature -40 to +85C
Parameter
Operating Voltage
Symbol
VDD
Conditions
Configuration Dependent
- See VersaClock
TM
Min.
3.15
Typ.
3.3
Max.
3.45
Units
V
mA
Operating Supply Current
Input High Voltage
IDD
33.3333 MHz output,
PDTS = 1, no load
Note 1
PDTS = 0
S1:S0
S1:S0
VDD-0.5
11
mA
20
2
0.4
0.4
Input High Voltage
Input Low Voltage
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
Input Low Voltage
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
Internal pull-up resistor
Internal pull-up resistor
Internal pull-down resistor
Input Capacitance
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Z
O
R
PUP
R
PUP
R
PD
C
IN
A
V
V
V
V
V
VDD/2-1
V
V
V
0.4
V
mA
k
k
k
pF
ICLK
ICLK
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12 mA
VDD/2+1
VDD-0.4
2.4
±70
20
S1:S0
PDTS
CLK output
inputs
250
250
525
4
Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V.
IDT® / ICS™
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
5
ICS341
REV N 072816
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