DATASHEET
SERIALLY PROGRAMMABLE CLOCK SOURCE
Description
The ICS307-03 is a dynamic, serially programmable clock
source which is flexible and takes up minimal board space.
Output frequencies are programmed via a 3-wire SPI port.
An advanced PLL coupled to an array of configurable
output dividers and three outputs allows low-jitter
generation of frequencies from 200 Hz to 270 MHz.
The device can be reprogrammed during operation, making
it ideal for applications where many different frequencies
are required, or where the output frequency must be
determined at run time. Glitch-free frequency transitions,
where the clock period changes slightly over many cycles,
are possible.
ICS307-03
Features
•
•
•
•
•
•
•
•
Crystal or clock reference input
3.3 V CMOS outputs
Three outputs can be individually configured or shut off
Small 16-pin TSSOP package – Pb-free, RoHS
compliant
Reprogrammable during operation
3-wire SPI serial interface
Glitch-free output frequency switching
User selectable charge pump current and damping
resistor
bit
•
Power-down control via hardware pin or software control
•
Programming word can be generated by IDT VersaClock
II Software
•
Directly programmable via VersaClock II Software and a
Windows PC parallel port
•
Industrial temperature range available
Block Diagram
Charge Pump
(Table 3)
(Table 1)
X1
[Bit 122]
X2
VCO DIVIDE
12-2055
(Table 2)
1
0
DIN
CS
SCLK
Programming
Register
(132 bits)
[Bit 123]
Divider
2 - 34
(Table 6)
[Bit 111]
CLK2
REF Divide
1-2055
Resistor
(Table 4)
300
pF
Divider
2 - 8232
(Table 5)
[Bit 110]
CP
11pF
CLK1
1
0
[Bit 124]
Divider
2 - 34
(Table 7)
[Bit 129]
CLK3
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE
1
ICS307-03
REV L 032911
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Pin Assignment
X1
VDD
VDD
VDD
GND
GND
GND
CLK1
1
2
3
16
15
14
X2
PD
CLK3
GND
CLK2
DIN
CS
SCLK
ICS307-03
4
5
6
7
8
13
12
11
10
9
16-pin TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X1
VDD
VDD
VDD
GND
GND
GND
CLK1
SCLK
CS
DIN
CLK2
GND
CLK3
PD
X2
XI
Power
Power
Power
Power
Power
Power
Output
Input
Input
Input
Output
Power
Output
Input
-
Connect to input reference clock or crystal.
Power connection for crystal oscillator.
Power connection for PLL.
Power connection for inputs and outputs.
Ground connection for crystal oscillator.
Ground connection for PLL.
Ground connection for inputs and outputs.
Clock 1 output.
Programming interface - Serial clock input. Internal pull-up.
Programming interface - LOAD input. Internal pull-down.
Programming interface - Serial data input. Internal pull-up.
Clock 2 output.
Ground connection.
Clock 3 output.
Crystal, PLL, and outputs are powered-down when low. Internal pull-up.
Connect to crystal. Leave open if reference clock input is used.
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE
2
ICS307-03
REV L 032911
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 1. Input Divider
Divide Value
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
…
2054
2055
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
Bits
6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
5
X
X
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
4
X
X
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
3
X
X
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
2
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
subtract 8 from the
desired divide value,
convert to binary, and
apply to bits 11...2
Bits [1..0] = 11
Rule
1+ Bit 0
1 + Bit 0
subtract 2 from the
desired value, convert to
binary, invert, and apply
to bits 5...2
Bits [1..0] = 10
Table 2. VCO Divider
Bits
Divide Value
12
13
14
2054
2055
…
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE
3
ICS307-03
REV L 032911
23
0
0
0
22
0
0
0
21
0
0
0
20
0
0
0
19
0
0
0
18
0
0
0
17
0
0
0
16
0
0
0
15
1
1
1
14
0
0
1
13
0
1
0
Rule
subtract 8 from the desired
divide value, convert to
binary, and apply to bits
23...13
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 3. Charge Pump Current (I
CP
)
Charge Pump Current (μA)
1.25
2.5
2.5
3.75
3.75
5
5
5
6.25
7.5
7.5
7.5
8.75
10
10
10
11.25
12.5
15
15
15
17.5
18.75
20
20
22.5
25
26.25
30
30
35
40
93
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
92
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
0
0
Bits
91
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
0
128
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
127
0
0
1
0
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
1
Rule
Icp = ([128...127]+1)*1.25μA*([93 92 91] + 1)
Table 4. Loop Filter Resistor (R
S
)
Bits
Resistor Value
64 k
52 k
16 k
4k
90
0
0
1
1
89
0
1
0
1
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE
4
ICS307-03
REV L 032911
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 5. Output Divider for Output 1
Divide
Value
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bits
109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 Rule
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
1
X
1
X
1
1
X
X
X
X
X
X
1
X
1
X
1
X
0
0
X
X
X
X
X
X
1
X
0
X
0
X
1
1
X
X
X
X
X
0
0
0
1
1
0
1
1
1
0
0
1
X
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
0
0
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
subtract 6 from the desired divide
value, convert to binary, invert, and
apply to bits 102..98
set bits [97..95] = 100
36
37
38
39
1029
1030
1032
2056
2058
2060
2064
4112
4116
4120
4128
8224
8232
…
…
…
…
X
X
0
0
X
X
0
0
X
X
0
0
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(increments of 1)
1
1
1
0
1
1
0
1
1
(increments of 2)
1
1
1
1
1
1
0
1
1
0
1
1
(increments of 4)
1
1
1
1
1
1
0
1
1
0
1
1
(increments of 8)
1
1
1
1
1
1
output divide =
((([109..101]+3)*2)+[98])*2^[100..99]
set bits [95..97] = 101
set bits [95..97] = 101
†
(
†
this Rule applies to Divide Values
38-8232)
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE
5
ICS307-03
REV L 032911
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