DS26401N+ datasheet, PDF - EEWORLD Datasheet

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DS26401N+: Descriptionnetwork controller & processor ics octal T1/E1/J1 framer; CategoryWireless rf/communication Telecom circuit; File Size1MB，309 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

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DS26401N+ Overview

network controller & processor ics octal T1/E1/J1 framer

DS26401N+ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Maxim
Reach Compliance Code	compli
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Telecom integrated circuit types	FRAMER
Maximum time at peak reflow temperature	NOT SPECIFIED

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DS26401

Octal T1/E1/J1 Framer

www.maxim-ic.com

GENERAL DESCRIPTION

The DS26401 is an octal, software-selectable T1, E1

or J1 framer. It is composed of eight framer/formatters

and a system (backplane) interface. Each framer has

an HDLC controller that can be mapped to any DS0

or FDL (T1)/Sa (E1) bit. The DS26401 also includes a

full-feature BERT device, which can be used with any

of the eight T1/E1 ports, and an internal clock adapter

useful for creating synchronous, high frequency

backplane timing. The DS26401 is controlled through

an 8-bit parallel port that can be configured for

nonmultiplexed Intel or Motorola operation.

FEATURES

8 Independent, Full-Featured T1/E1/J1

Framers/Formatters

Independent Transmit and Receive Paths

Flexible Signaling Extraction and Insertion

Alarm Detection and Insertion

Transmit Synchronizer

AMI, B8ZS, HDB3, NRZ Line Coding

Performance Monitor Counters

BOC Message Controller (T1)

Two-Frame Elastic Store Buffers for Each

Transmitter and Receiver

One HDLC Controller per Framer

RAI-CI and AIS-CI Support

Full-Feature BERT can be Mapped to Any Port

Flexible TDM Backplane Supports Bus Rates

from 1.544MHz to 16.384MHz

Internal Clock Generator (CLAD) Supplies

16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz

JTAG Test Port

Single 3.3V Supply with 5V Tolerant Inputs

17mm x 17mm, 256-Pin BGA (1.00mm Pitch)

APPLICATIONS

Line Cards

Add-Drop Multiplexers

DSLAMs

Timing Systems

PBXs

Switches

Central Office Equipment

Go to

www.maxim-ic.com/telecom

for a complete list of

Telecommunications data sheets, evaluation kits, application

notes, and software downloads.

Routers

IMA

ATM

WAN Interface

Customer-Premise

Equipment

ORDERING INFORMATION

PART

DS26401

DS26401N

TEMP RANGE

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

256 BGA

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

REV: 072403

DS26401 Octal T1/E1/J1 Framer

LIST OF FIGURES

Figure 3-1. Block Diagram ........................................................................................................................................10

Figure 3-2. Typical PLL Connection..........................................................................................................................11

Figure 3-3. Typical Bipolar Network-Side Interface to Framers................................................................................11

Figure 3-4. Typical NRZ Network-Side Interface to Framers....................................................................................12

Figure 7-1. Internal IBO Multiplexer Equivalent Circuit—4.096MHz .........................................................................28

Figure 7-2. Internal IBO Multiplexer Equivalent Circuit—8.192MHz .........................................................................29

Figure 7-3. Internal IBO Multiplexer Equivalent Circuit—16.394MHz ......................................................................30

Figure 8-1. RSYNC Input in H.100 (CT Bus) Mode ..................................................................................................50

Figure 8-2. TSSYNC Input in H.100 (CT Bus) Mode ................................................................................................51

Figure 8-3. Receive HDLC Example........................................................................................................................99

Figure 9-1. HDLC Message Transmit Example .....................................................................................................141

Figure 10-1. RSYNC Input in H.100 (CT Bus) Mode ..............................................................................................162

Figure 10-2. TSSYNC Input in H.100 (CT Bus) Mode ............................................................................................163

Figure 10-3. Receive HDLC Example....................................................................................................................207

Figure 11-1. HDLC Message Transmit Example ....................................................................................................255

Figure 12-1. Shared BERT Block Diagram .............................................................................................................266

Figure 13-1. T1 Receive-Side D4 Timing ...............................................................................................................277

Figure 13-2. T1 Receive-Side ESF Timing .............................................................................................................277

Figure 13-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) .............................................................278

Figure 13-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................278

Figure 13-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................279

Figure 13-6. T1 Receive-Side Interleave Bus Operation, BYTE Mode...................................................................280

Figure 13-7. T1 Receive-Side Interleave Bus Operation, FRAME Mode................................................................281

Figure 13-8. T1 Transmit-Side D4 Timing ..............................................................................................................282

Figure 13-9. T1 Transmit-Side ESF Timing ............................................................................................................282

Figure 13-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) ...........................................................283

Figure 13-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ..........................................283

Figure 13-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ..........................................284

Figure 13-13. T1 Transmit-Side Interleave Bus Operation, BYTE Mode................................................................284

Figure 13-14. T1 Transmit Interleave Bus Operation, FRAME Mode.....................................................................285

Figure 13-15. E1 Receive-Side Timing ...................................................................................................................286

Figure 13-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................286

Figure 13-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ...........................................287

Figure 13-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ...........................................287

Figure 13-19. E1 Transmit-Side Timing..................................................................................................................288

Figure 13-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)...........................................................288

Figure 13-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) .........................................289

Figure 13-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ..........................................289

Figure 13-23. E1 G.802 Timing...............................................................................................................................290

Figure 15-1. Intel Bus Read Timing (BTS = 0).......................................................................................................293

Figure 15-2. Intel Bus Write Timing (BTS = 0).......................................................................................................293

Figure 15-3. Motorola Bus Read Timing (BTS = 1) ...............................................................................................294

Figure 15-4. Motorola Bus Write Timing (BTS = 1) ...............................................................................................294

Figure 15-5. Receive Framer Timing—Backplane (T1 Mode)...............................................................................295

Figure 15-6. Receive-Side Timing—Elastic Store Enabled (T1 Mode)..................................................................296

Figure 15-7. Receive Framer Timing—Line Side ..................................................................................................297

Figure 15-8. Transmit Formatter Timing—Backplane ...........................................................................................299

Figure 15-9. Transmit Formatter Timing, Elastic Store Enabled ...........................................................................300

Figure 15-10. Transmit Formatter Timing—Line Side ...........................................................................................300

Figure 15-11. JTAG Interface Timing Diagram.......................................................................................................301

Figure 16-1. JTAG Functional Block Diagram ........................................................................................................302

Figure 16-2. Tap Controller State Diagram............................................................................................................303

DS26401N+ Related Products

	DS26401N+	DS26401NA2+	DS26401A2+
Description	network controller & processor ics octal T1/E1/J1 framer	network controller & processor ics octal T1/E1/J1 framer	IC OCTAL FRAMER T1/E1/J1 256BGA
Is it lead-free?	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to
Maker	Maxim	Maxim	Maxim
Reach Compliance Code	compli	compli	compliant
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Telecom integrated circuit types	FRAMER	FRAMER	FRAMER
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED

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