SL15300
Programmable Spread Spectrum Clock Generator (SSCG)
Key Features
•
Low power dissipation
- 7.9mA-typ at 66MHz and VDD=3.3V
- 7.0mA-typ at 66MHz and VDD=2.5V
Wide 2.5V to 3.3V +/-10% power supply range
Programmable 4 outputs from 3 to 200MHz
Low Jitter
- TBDps at 66MHz
Programmable Center or Down Spread Modulation
from 0.25 to 5.0%
8 to 48 MHz external crystal range
8 to 166 MHz external clock range
Integrated internal voltage regulator
Programmable PD#/OE/SSON#/FS functions
Programmable CL at XIN and XOUT pins
Programmable output rise and fall times
SSC modulation frequency is 32kHz-typ
Printers, MFPs
Digital Copiers
NBPCs and LCD Monitors
Routers, Servers and Switchers
HDTV and DVD-R/W
Description
The SL15300 a programmable low power Spread
Spectrum Clock Generator (SSCG) used for reducing
Electromagnetic Interference (EMI). The product is
designed using SpectraLinear proprietary programmable
EProClock™
phase-locked loop (PLL) and Spread
Spectrum Clock (SSC) technology to synthesize and
modulate the input clock. The modulated clock can
significantly reduce the measured EMI levels, and leading
to the compliance with regulatory agency requirements.
Up to 4 output clock frequencies, Spread %, output rise
and fall times, crystal load, modulation frequency and
PD#/OE/SSON#/FS functions can be programmed to meet
the needs of wide range of applications. The SL15300
operates from 2.5V to 3.3V power supply voltage range.
The product is offered in 8-pin TSSOP package with
commercial and industrial grades.
Refer to SL15L300 Programmable SSCG product for 1.8V
power supply operation.
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Applications
Benefits
•
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Peak EMI reduction of 8 to 16 dB
Fast time-to-market
Cost Reduction
Reduction of PCB layers
Eleminates the need for higher order crystals (Xtals)
and crystal oscillators (XOs)
Block Diagram
300K
XIN/CLKIN
3
PCin
PLL with
Modulation Control
Output
Buffers,
Dividers
and
Switch
Matrix
7
CLKOUT
XOUT
2
PCout
6
REFOUT
To I/O
VDD
VSS
1
5
Programmable
Configuration Register
To
Core
V-Reg
4
PD#
8
SSON#
Rev 2.0, October 11, 2010
Page 1 of 16
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL15300
General Description
The primary source of EMI from digital circuits is the
system clock and all the other synchronous clocks and
control signals derived from the system clock. The well
know techniques of filtering (suppression) and shielding
(containment), while effective, can cost money, board
space and longer development time.
A more effective and efficient technique to reduce EMI is
Spread Spectrum Clock Generator (SSCG) technique.
Instead of using constant clock frequency, the SSCG
technique modulates (spreads) the system clock with a
much smaller frequency, to reduce EMI emissions at its
source: The System Clock.
The SL15300 is designed using SpectraLinear
proprietary programmable
EProClock™
phase-locked
loop (PLL) and Spread Spectrum Technologies (SST) to
synthesize and modulate (spread) the system clock such
that the energy is spread out over a wider bandwidth.
This reduces the peak value of the radiated emissions at
the fundamental and the harmonics. This reduction in
radiated energy can significantly reduce the cost of
complying with regulatory agency requirements and
improve time-to-market without degrading system perfor-
mance.
The SL15300 operates from 3.3V to 2.5V power supply
range. Refer to SL15L101 for 1.8V power supply
operation.
The SL15300 is available in 8-pin TSSOP package with
Commercial Temperature range of 0 to 70°C and
Industrial Temperature range of –40 to 85°C.
Input Frequency Range
The input frequency range is from 8.0 to 48.0 MHz for
crystals and ceramic resonators. If an external clock is
used, the input frequency range is from 8 to 166 MHz.
Output Frequency Range and Outputs
Up to four (4) outputs can be programmed as SSCLK or
REFCLK. SSCLK output can be synthesized to any value
from 3 to 200 MHz with spread based on valid input
frequency. The spread at SSCLK pins can be stopped by
SSON# input control pin, If SSON# pin is HIGH (VDD),
the frequency at this pin is the synthesized to the
nominal value of the input frequency and there is no
spread.
REFOUT is the buffered output of the oscillator and is
the same frequency as the input frequency without
spread. However, REFOUT value can also be divided by
using the output dividers from 2 to 32. The SSCLK is the
programmed and synthesized value of the input clock.
The remaining SSCLKs could be the same value
providing fanout of up to 4 or the frequency can be
divided from also 2 to 32. In this case, the spread %
value is the same as the original programmed spread %
value. By using only first order crystals, SL15300 can
synthesize output frequency up to 200 MHz, eliminating
the need for higher order Crystals (Xtals) and Crystal
Oscillators (XOs). This reduces the cost while improving
the system clock accuracy, performance and reliability.
Rev 2.0, October 11, 2010
Programmable CL (Crystal Load)
The SL15300 provides programmable on-chip capacitors
at XIN/CLKIN (Pin-3) and XOUT (Pin-2). The resolution of
this programmable capacitor is 6-bits with LSB value of
0.5pF. When all bits are off the pin capacitance is
CXIN=CXOUT =8.5pF (minimum value). When all bits are
on the pin capacitance is CXIN=CXOUT=40pF (maximum
value). The values of C
XIN
and C
XOUT
based on the C
L
(Crystal Load Capacitor) can be calculated as:
C
XIN
=C
XOUT
=2C
L
-C
PCB
. Refer to the Page-13 for
additional information on crystal load (C
L
).
In addition, if an external clock is used, the capacitance at
Pin-3 (CLKIN) can programmed to control the edge rate of
this input clock, providing additional EMI control.
Programmable Modulation Frequency
The Spread Spectrum Clock (SSC) modulation default
value is 31.5 kHz. The higher values of up to 120 kHz can
also be programmed. Less than 30 kHz modulation
frequency is not recommended to stay out of the range
audio frequency bandwidth since this frequency could be
detected as a noise by the audio receivers within the
vicinity.
Programmable Spread Percent (%)
The spread percent (%) value is programmable from +/-
0.25% to +/-2.5% (center spread) or -0.5% to -5.0%
(down spread) for all SSCLK frequencies. It is possible to
program smaller or larger non-standard values of spread
percent. Contact SLI if these non-standard spread percent
values are required in the application.
SSON# or Frequency Select (FS)
The SL15300 Pin-8 can also be programmed as either
SSON# to enable or disable the programmed spread
percent value or as Frequency Select (FS). If SSON# is
used, when this pin is pulled high (VDD), the spread is
stopped and the frequency is the nominal value without
spread. If low (GND), the frequency is the nominal value
with the spread.
If FS function is used, the output pins can be programmed
for different set of frequencies as selected by FS. SSCLK
value can be any frequency from 3 to 200MHz, but the
spread % is the same percent value. REFOUT is the
same frequency as the input reference clock or divide by
from 2 to 32 without spread. The set of frequencies in
Table 1 is given as en example, using 48MHz crystal.
The SL15300 also allows a fan-out of up to 4, meaning
that Pins 4, 6, 7 and 8 can be programmed to the same
frequencies with or without spread.
FS
(Pin-8)
0
1
SSCLK1/2
(Pins-6/7)
66MHz, +/-2%
33MHz, +/-2%
REFCLK4
(Pin-4)
48MHz
24MHz
Table 1. Frequency Selection (FS)
Power Down (PD#) or Output Enable (OE)
The SL15300 Pin-4 can be programmed as either PD# or
OE. PD# powers down the entire chip whereas OE only
disables the output buffers to Hi-Z.
Page 3 of 16
SL15300
Absolute Maximum Ratings
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Rating (Human Body Model)
JEDEC22-A114D
In operation, C-Grade
In operation, I-Grade
No power is applied
In operation, power is applied
Condition
Min
-0.5
-0.5
0
-40
-65
-
-
-4,000
-1,500
-250
-200
Max
4.6
VDD+0.5
70
85
150
125
260
4,000
1,500
250
200
Unit
V
V
°C
°C
°C
°C
°C
V
V
V
mA
ESD Rating (Charge Device Model)
JEDEC22-C101C
ESD Rating (Machine Model)
Latch-up
JEDEC22-A115D
125°C
DC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70 Deg C
Description
Operating Voltage
Input Low Voltage
Symbol
VDD
VIL
Condition
VDD+/-10%
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS.
IOH=10mA , If Pins 4, 6, 7 and
8 are programmed as
SSCLK/REFCLK
IOL=10mA, If Pins 4, 6, 7 and 8
are programmed as
SSCLK/REFCLK
VIN=VDD, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
VIN=GND, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS
Min
2.97
0
Typ
3.3
-
Max
3.63
0.3VDD
Unit
V
V
Input High Voltage
VIH
0.7VDD
-
VDD
V
Output High Voltage
VOH1
VDD-0.5
-
-
V
Output Low Voltage
VOL1
-
-
0.5
V
Input High Current
IIH
-10
-
10
μA
Input Low Current
IIL
-10
-
10
μA
Pull-up or Down Resistors
RPU/D
90
160
230
kΩ
Rev 2.0, October 11, 2010
Page 4 of 16
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