SL28SRC02
PCI Express Gen 2 & Gen 3 Clock Generator
Features
• Low power PCI Express Gen 2 & Gen 3 clock generator
• Two100-MHz differential SRC clocks
• Low power push-pull output buffers (no 50ohm to
ground needed)
• Integrated 33ohm series termination resistors
• Low jitter (<50pS)
• SSON input for enabling spread spectrum clock
• I
2
C support with readback capabilities
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Input frequency of 14.318MHz
• Industrial Temperature -40
o
C to 85
o
C
• 3.3V power supply
• 20-pin TSSOP package
Block Diagram
Pin Configuration
VDD 1
14.318MHz
crystal or clock
Crystal
Oscillator/
clock buffer
20 XIN
19 XOUT
18 VSS
17 SSON
16 VDD
15 VSS
14 VDD
13 VDD
12 SRC2#
11 SRC2
SRC1
SDATA 2
SCLK 3
VDD 4
VSS 5
VDD 6
VSS 7
SRC1 8
SRC1# 9
VSS 10
PLL
SRC1#
SRC2
SSON
Control
logic
SRC2#
.................................................... Document #: Page 1 of 14
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL28SRC02
Pin Definitions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VDD
SDATA
SCLK
VDD
VSS
VDD
VSS
SRC1
SRC1#
VSS
SRC2
SRC2#
VDD
VDD
VSS
VDD
SSON
VSS
XOUT
XIN
Name
Type
PWR
I/O
I
PWR
GND
PWR
GND
Description
3.3V Power supply
SMBus compatible SDATA.
SMBus compatible SCLOCK.
3.3V power supply
Ground
3.3V power supply
Ground
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
GND
Ground
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
PWR
PWR
GND
PWR
I
GND
I
3.3V power supply
3.3V power supply
Ground
3.3V power supply
3.3V LVTTL input for enabling spread spectrum clock
0 = Disable, 1 = Enable (-0.5% SS)
External 10K ohm pull-up or pull-down resistor required
Ground
14.318 MHz Crystal input.
O, SE 14.318 MHz Crystal output.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
.................................................... Document #: Page 2 of 14
SL28SRC02
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
.................................................... Document #: Page 3 of 14
SL28SRC02
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
HW
0
1
0
0
0
0
1
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
0
0
0
1
0
1
Name
RESERVED
PLL1_SS_DC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Select for down or center SS
0 = Down spread, 1 = Center spread
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
.................................................... Document #: Page 4 of 14
SL28SRC02
Byte 4: Control Register 4
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
RESERVED
SRC1_OE
SRC2_OE
RESERVED
RESERVED
RESERVED
PLL1_SS_EN
RESERVED
RESERVED
Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC2
0 = Output Disabled, 1 = Output Enabled
RESERVED
RESERVED
RESERVED
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
RESERVED
Description
Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Byte 6: Control Register 6
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Byte 7: Vendor ID
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
1
1
1
0
0
0
Name
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
.................................................... Document #: Page 5 of 14
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