Intel
®
Communications Chipset 89xx
Series
Datasheet
April 2014
Order Number: 327879-005US
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Copyright © 2014, Intel Corporation. All Rights Reserved.
Intel
®
Communications Chipset 89xx Series - Datasheet
2
April 2014
Order Number: 327879-005US
Revision History
Revision History
Date
Revision
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Description
Updated
Section 1.1
Introduction
Updated
Table 1-1
added DH8926CL.
Updated
Section 1.2
added bullets.
Added
Section 1.2.
Differences Between DH89xxCC and DH89xxCL SKUs.
Added
Table 1-2.
Differences Between DH89xxCC and DH89xxCL SKUs.
Correction to
Table 3-3.
Clarification to
Table 5-4.
Clarified note,
Section 6.9.1.4.
Correction to
Table 6-137
through
Table 6-139
and
Table 6-142.
Correction to
Table 8-1
and
Table 8-3.
Added table footnote to
Table 9-3.
Added table footnote to
Table 10-1
Corrected to
Table 10-3.
Added table footnote to
Table 11-1.
Corrected table
Table 11-3.
Added table footnote to
Table 17-1.
Corrected table
Table 17-3.
Corrected note,
Table 19-3.
Correction to
Table 20-23.
Corrected SKU values & Added DH8926CL.
Added clarifications to
Table 32-1.
Correction to
Table 32-2.
Added
Table 32-22
Footnote 5 and Table Note.
Added
Table 33-2
Footnote for DH89xxCC maximum voltage.
Corrected
Figure 33-19.
GBE_EE_DO & GBE_EE_DI were reversed.
Added Chipset references 8903, 8910, 8920, 8925, 8950, and 8955 to
Section 33.0.
Updated
Table 3-3.
Added DH89xxCL Device IDs.
Updated
Table 3-4.
Added DH89xxCL Device IDs.
Updated
Section 19.2.3.1.
Updated
Table 1-1.
Added DH8925CL, DH8950CL & DH8955CL SKUs.
Updated
Figure 2-2
to include the Added DH8925CL, DH8950CL & DH8955CL features.
Updated
Table 2-1
to include the Added DH8925CL, DH8950CL & DH8955CL features.
Correction to
Table 4-4.
Updated
Table 4-22.
Changed “CPUSCI_STS” to DMISCI_STS”.
Updated
Table 4-22.
Changed “OS_TCO_SMI” to “SW_TCO_SMI”.
Updated
Section 4.12.3.2.
Updated
Section 6.6.1
Changed “he” to “the”.
Updated
Table 7-65.
Changed “0062003h” to “06200003h”.
Updated
Table 7-66.
Changed bit field description.
Updated
Table 12-49.
Changed “DMI” to “Root Port”.
Updated
Section 20.2.2.18.
Updated
Chapter 21.0.
Added note in the introduction.
Corrected typo in
Section 22.5.2.2.
Updated
Section 24.11.6
Updated
Section 28.7.1.23.
Changed “Section 28-62” to “Table
28-62”.
Updated
Chapter 32.0
to include the Added DH8925CL, DH8950CL & DH8955CL.
March 2014
005
December
2013
004
December
2013
003
April 2014
Order Number: 327879-005US
Intel
®
Communications Chipset 89xx Series - Datasheet
3
Date
Revision
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Description
July 2013
002
Updated
Table 3-3.
Deleted “SATA* Controller 1 Desktop: in IDE, supporting 2 ports; DID =
0x2321”. Added operational support details for SATA* Controller #1 and SATA* Controller #2.
Updated
Section 4.10.1.5
and
Table 4-32.
Changed “PROCPWRGD” to “CPUPWRGD”
Updated
Section 4.15.
Changed “ACHI” to “AHCI”
Updated
Section 4.5.1.
Changed “ACHI” to “AHCI”; and added PCIe* B:D:F mapping details for
SATA* Controllers #1 and #2.
Updated
Section 4.15.7.
Changed Section Title from “ATA LED” to “SATA* LED”
Updated
Figure 4-22.
Changed “ECHI” to “EHCI”
Updated
Section 10.2.2.9.
Removed Port(x) Offset Address Mapping for when RMH is disabled
since RMH is always enabled.
Updated
Table 12-4;
Offset 04h: PCI COMMAND Register. Re-assigned Register Bits to sync with
PCIe* Specification Register Bit definitions.
Updated
Table 20-10
Assigned the correct Major and Minor Revision default values for the
chipset.
Updated
Table 21-1.
Refined the definition of EEPROM.
Updated
Section 21.5.
Added a Note to define “FLEEP”
Updated
Section 22.5.2.2.2
Added wording to indicate that Ownership Acquisition of Shared
Resources is required before MDIC Read/Write cycles can be executed.
Updated
Section 22.5.6.2.1
Added correct setting of CTRL_EXT.LINK_MODE for MAC Loopback.
Updated
Section 24.3.12
“LED 0 Configuration Defaults (LAN Base Address + Offset 0x1F)”.
Updated cross-references for the EEPROM Word
Updated
Section 24.3.13“Software
Defined Pins Control (LAN Base Address + Offset 0x20)”.
Added Description Clarification Notes to Bit[11] and Bit[10]
Updated
Table 28-9
In the Note for For Bit[7], removed reference to LAN_PWR_GOOD.
Updated
Table 28-14.
New definition for Bit[31] = ‘0b’.
Updated
Table 28-15.
All bits are “Reserved”, except Bit[2].
Updated
Section 28.17.1.8
Added
Table 28-184,
“SFP I2C Command - I2CCMD [0:3] (0x1028;
R/W)”
Updated
Table 32-8.
Specification Update for GBE[0:3]_LED configuration straps. External strap
requirement.
Updated
Table 32-22.
Changed “Native” Default Mode to “GPIO”
Updated
Table 32-27.
Updated strap requirements for GBE[0:3]_LED Signals
Updated
Table 32-29
Updated Description for VCC3P3_RTC
Updated
Table 33-2.
Updated VCC3P3_RTC and VCC3P3_RTC (Battery) min/max Power Rail
values. Added Note for VCC3P3_RTC voltage requirement specification.
Updated
Table 33-3.
Removed Table Note 1- “Pre-silicon estimates and subject to change”
Updated
Table 33-9.
Updated IOL(max) for VOL7 and VOL8 (JTDO / EP_JTDO Output Low)
Updated
Table 33-25.
Removed AC coupling capacitor for GbE Clock (GBE_CLK100[P,N])
Updated
Table 33-29.
Updated the minimum (min) values for t188a (SPI_CLK high time) and
t189a (SPI_CLK low time) for SPI Timings (20MHz).
Updated
Table 33-1
through
Table 33-5.
August 2012
001
•
Intel
®
Communications Chipset 89xx Series - Datasheet
4
April 2014
Order Number: 327879-005US
Revision History
Product Features
Platform Controller Hub (PCH)
— Integrated Intel
®
Platform Controller Hub Complex
technology
— Intel Architecture Processor Companion
— Asynchronous DIMM Refresh (ADR)
— Intel
®
QuickAssist Technology
— Extensive integration of standard Intel architecture
communications interfaces provide cost, power
and board area savings
Intel
®
QuickAssist Integrated Accelerator
— Symmetric Cryptographic Functions
— Public Key Functions
— Compression/Decompression
Direct Media Interface (DMI) Gen1
— 10 Gb/s each direction, full duplex
— Transparent to software
PECI Interface
PCI Express* Gen1
— 4 PCI Express* Root Complex Ports
— PCIe* Gen1 speed (2.5GT/s)
— Compliant to Gen2 messaging protocol
— Ports can be independently configured to support
4x1, 2x2, 1x2 + 2x1, or 1x4
— Supports lane reversal with x4 configuration
— Module based Hot-Plug supported (for example,
ExpressCard*)
Integrated Serial ATA Host Controller
— Two SATA* ports
— SATA* Gen2 Data transfer rates up to 3.0 Gb/s
(300 MB/s).
— One activity LED
— Multiple MSI Message vectors.
— Integrated AHCI controller
USB* 2.0/1.1
— Six USB* 1.1 or USB* 2.0
— One EHCI Host Controller, supporting up to six
external ports.
— Per-Port-Disable Capability
— Includes two USB* 2.0 High-speed Debug Ports
— Supports wake-up from sleeping states S1-S4
— Supports legacy Keyboard/Mouse software
UART
— Two integrated UARTs 16550 compatible
SMBus
— SMBus Interfaces
— One Host SMBus (Master)
— One SMLINK (Slave)
— One EndPoint SMBus (Slave)
— One GbE SMBus (Master/Slave)
— SMBus Max speed, up to 100 KHz
— Supports SMBus 2.0 Specification
— Host interface allows processor to communicate
via SMBus
— Slave interface allows an internal or external
microcontroller to access system resources
— Compatible with most two-wire components that
are also I2C compatible
High Precision Event Timers
— Advanced operating system interrupt scheduling
Timers Based on 82C54
— System timer, Refresh request, Speaker tone
output
Real-Time Clock
— 256-byte battery-backed CMOS RAM
— Integrated oscillator components
— Lower Power DC/DC Converter implementation
System TCO Reduction Circuits
— Timers to generate SMI# and Reset upon
detection of system hang
— Timers to detect improper processor reset
— Integrated processor frequency strap logic
— Supports ability to disable external devices
Serial Peripheral Interface (SPI)
— Supports up to two SPI devices
— Two Chip Select pins, up to 16MB per memory
device.
— Supports 20/33/50 MHz SPI devices.
— Support up to two different erase granularities.
Interrupt Controller
— Supports SERIRQ interrupt pin
— Supports PCI 2.3 Message Signaled Interrupts
— Two cascaded 82C59 with 15 interrupts
— Integrated I/O APIC capability with 24 interrupts
— Supports Processor System Bus interrupt delivery
DMA Controller
— Two cascaded 8237 DMA controllers
— Supports LPC DMA
April 2014
Order Number: 327879-005US
Intel
®
Communications Chipset 89xx Series - Datasheet
5
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