Multilayer Ceramic Chip Capacitors
FEATURES
•
CLASS I DIELECTRIC, TEMPERATURE COMPENSATING
•
HIGH STABILITY OVER TIME, VOLTAGE AND
TEMPERATURE CHANGES
•
LOW DIELECTRIC LOSS
•
NICKEL BARRIER TERMINATIONS AND EXCELLENT
MECHANICAL STRENGTH
•
EIA MARKING AVAILABLE
SPECIFICATIONS NPO
Capacitance Range
Capacitance Tolerances
Operating Temperature Range
Temperature Characteristics
Rated Voltages
Dissipation Factor
Insulation Resistance
Dielectric Withstanding Voltage
Test Conditions (EIA-198-2E)
NMC Series NPO
SURFACE MOUNT
0.47pF to .056
µF
Below 10pF: ±0.1pF(B), ±.25pF(C), ±.5pF(D);
10pF and above: ±1%(F), ±2%(G), ±5%(J)
-55
o
C to +125
o
C
0 ± 30ppm/
o
C
25Vdc, 50Vdc, 100Vdc (see NMC-H Series for Higher Voltages)
For values >30pF 0.1% @25°C; For values<30pF Q=400+20xC (C in pF)
100,000 Mohms min. or 1000 Mohm -
µ
F (min.) whichever is less @ +25
o
C
250% of Rated Voltage for 5 ± 1 seconds, 50 milliamps maximum
≤
1000pF; 1Mhz, 1.2Vrms Max. or >1000pF; 1khz, 1.2Vrms Max.
TYPICAL NPO TEMPERATURE COEFFICIENT
% CAPACITANCE CHANGE
VOLTAGE COEFFICIENT OF
CAPACITANCE ~ NPO
0.2
0.1
MINIMUM INSULATION RESISTANCE
VS TEMPERATURE
10000
INSULATION RESISTANCE
(µFARADS)
1000
0.0
-0.1
-0.2
0 10 20 30 40 50 60 70 80 90 100
100
10
10
25
100
150
DC VOLTS APPLIED
Impedance vs. Frequency - NPO
% CAPACITANCE CHANGE
0.2
0.1
0.0
-0.1
-0.2
1
10
100
TEMPERATURE
O
C
Aging Rate - NPO
1000
10000
Hours
PART NUMBERING SYSTEM
NMC
0805
NPO
471
J
50
TRP or TRPLP
F
Lead Free Terminations
(100% Sn optional)
Tape and Reel (Embossed
Plastic Carrier)
Tape and Reel (Paper Carrier)
Voltage (Vdc)
Capacitance Tolerance Code (see chart above)
Capacitance Code, expressed in pF, first 2 digits are
significant, 3rd digit is no. of zeros, “R” indicates
decimal for under 10pF
Temperature Characteristic
®
Series
Size Code (see chart)
NIC COMPONENTS
www.niccomp.com
www.lowESR.com
www.RFpassives.com
137
Multilayer Ceramic Chip Capacitors
SURFACE MOUNT
NPO CAPACITOR SIZE CHART (mm)
(CONSULT FACTORY
FOR CAPACITANCE
VALUES NOT LISTED)
EIA Case Size
Length
L
Width
W
Thickness (max.) T
Termination Width P
Capacitance
0.47pF
1.0
1.5
2.2
2.7
3.3
4.7
6.8
8.2
10
12
15
18
20
22
27
33
39
47
56
68
82
100
120
150
180
220
270
330
390
470
560
680
820
1000
1500
1800
2200
2700
3300
4700
10
0201
0.6±0.03
0.3±0.03
0.3±0.03
0.15±0.05
16
25
50
NMC Series NPO
0402
0603
0805
1.0±0.05
1.6±0.15
2.0±0.2
0.5±0.05
0.8±0.15
1.25±0.2
0.6
1.0
1.30
0.2±0.1
.12-.51
.25-.71
Working Voltage
16 25 50 25 50 100 25 50 100
W
T (max.)
P
L
P
Termination:
Sn-Pb solder plate
finish over nickel
barrier over Ag base.
Also available with
100% Sn lead-free
plating finish.
®
138
NIC COMPONENTS
www.niccomp.com
www.lowESR.com
www.RFpassives.com
Multilayer Ceramic Chip Capacitors
NPO CAPACITOR SIZE CHART (mm)
EIA Case Size
Length
L
Width
W
Thickness (max.) T
Termination Width P
Capacitance
100
120
150
180
220
270
330
470
560
680
750
820
1000
1500
1800
2200
2700
3300
3900
4700
5600
6800
8200
.01
µF
.015
.018
.022
.027
.033
.039
.047
.056
25
1206
3.2±0.2
1.6±0.2
1.80
.25-.71
NMC Series NPO
SURFACE MOUNT
1210
1812
2225
3.2±0.2
4.5±0.3
5.7±0.4
2.5±0.2
3.2±0.25
6.35±0.25
1.80
1.80
1.80
.25-.71
.25-.76
.25-1.02
Working Voltage
50 100 25 50 100 25 50 100 25 50 100
®
NIC COMPONENTS
www.niccomp.com
www.lowESR.com
www.RFpassives.com
139
京公网安备 11010802033920号
EEWORLD
