5962R9662902VXC datasheet, PDF

5962R9662902VXC: Description4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAMIC, FP-16; Categorylogic logic; File Size138KB，24 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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5962R9662902VXC Overview

4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAMIC, FP-16

Parameter Name	Attribute value
Objectid	2082028747
Parts packaging code	DFP
package instruction	DFP, FL16,.3
Contacts	16
Reach Compliance Code	unknown
series	4000/14000/40000
JESD-30 code	R-CDFP-F16
JESD-609 code	e4
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Sup	2590000 Hz
MaximumI(ol)	0.00064 A
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL16,.3
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5/15 V
Prop。Delay @ Nom-Sup	405 ns
propagation delay (tpd)	405 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
Trigger type	POSITIVE EDGE
minfmax	2.59 MHz

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