RD28F3208C3T90 datasheet, PDF - EEWORLD Datasheet

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RD28F3208C3T90: Description3 VOLT INTEL Advanced+BootBlock FlashMemory(C3)Stacked-ChipScalPackageFamilye; Categorystorage storage; File Size726KB，70 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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RD28F3208C3T90 Overview

3 VOLT INTEL Advanced+BootBlock FlashMemory(C3)Stacked-ChipScalPackageFamilye

RD28F3208C3T90 Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	BGA
package instruction	LFBGA, BGA68,8X12,32
Contacts	66
Reach Compliance Code	unknown
Maximum access time	90 ns
Other features	SRAM IS ORGANIZED AS 512K X 16
JESD-30 code	R-PBGA-B66
length	10 mm
memory density	33554432 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Mixed memory types	FLASH+SRAM
Number of functions	1
Number of terminals	66
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA68,8X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
power supply	3 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.000006 A
Maximum slew rate	0.055 mA
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	8 mm
Base Number Matches	1

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3 Volt Intel

Advanced+ Boot Block

Flash Memory (C3) Stacked-Chip Scale

Package Family

Datasheet

Product Features

■

Flash Memory Plus SRAM

— Reduces Memory Board Space

Required, Simplifying PCB Design

Complexity

Stacked-Chip Scale Package (Stacked-

CSP) Technology

— Smallest Memory Subsystem Footprint

— Area : 8 x 10 mm for 16Mbit (0.13 µm)

Flash + 2Mbit or 4Mbit SRAM

— Area : 8 x 12 mm for 32Mbit (0.13 µm)

Flash + 4Mbit or 8Mbit SRAM

— Height : 1.20 mm for 16Mbit (0.13 µm)

Flash + 2Mbit or 4Mbit SRAM and

32Mbit (0.13um) Flash + 8Mbit SRAM

— Height : 1.40 mm for 32Mbit (0.13 µm)

Flash + 4Mbit SRAM

— This Family also includes 0.25 µm and

0.18 µm technologies

Advanced SRAM Technology

— 70 ns Access Time

— Low Power Operation

— Low Voltage Data Retention Mode

Intel

Flash Data Integrator (FDI)

Software

— Real-Time Data Storage and Code

Execution in the Same Memory Device

— Full Flash File Manager Capability

■

Advanced+ Boot Block Flash Memory

— 70 ns Access Time at 2.7 V

— Instant, Individual Block Locking

— 128 bit Protection Register

— 12 V Production Programming

— Ultra Fast Program and Erase Suspend

— Extended Temperature –25 °C to +85 °C

Blocking Architecture

— Block Sizes for Code + Data Storage

— 4-Kword Parameter Blocks (for data)

— 64-Kbyte Main Blocks (for code)

— 100,000 Erase Cycles per Block

Low Power Operation

— Async Read Current: 9 mA (Flash)

— Standby Current: 7 µA (Flash)

— Automatic Power Saving Mode

Flash Technologies

— 0.25 µm ETOX™ VI, 0.18 µm ETOX™

VII and 0.13 µm ETOX™ VIII Flash

Technologies

— 28F160xC3, 28F320xC3

The 3 Volt Intel

Advanced+ Boot Block Flash Memory (C3) Stacked-Chip Scale Package

(Stacked-CSP) device delivers a feature-rich solution for low-power applications. The C3

Stacked-CSP memory device incorporates flash memory and static RAM in one package with

low voltage capability to achieve the smallest system memory solution form-factor together with

high-speed, low-power operations. The C3 Stacked-CSP memory device offers a protection

the Intel

Flash Data Integrator (Intel

FDI) software, the C3 Stacked-CSP memory device

provides a cost-effective, flexible, code plus data storage solution.

Notice:

This document contains information on new products in production. The specifications

are subject to change without notice. Verify with your local Intel sales office that you have the lat-

est datasheet before finalizing a design.

252636-001

February, 2003

Contents

1.0

Introduction....................................................................................................................................7

1.1

1.2

1.3

1.4

2.0

2.1

Document Conventions ........................................................................................................7

Product Overview .................................................................................................................7

Package Ballout....................................................................................................................8

Signal Definitions ..................................................................................................................9

Bus Operation .....................................................................................................................11

2.1.1 Read ......................................................................................................................11

2.1.2 Output Disable .......................................................................................................12

2.1.3 Standby..................................................................................................................12

2.1.4 Flash Reset............................................................................................................13

2.1.5 Write ......................................................................................................................13

Read Array (FFh) ................................................................................................................13

Read Identifier (90h) ...........................................................................................................13

Read Status Register (70h) ................................................................................................14

3.3.1 Clear Status Register (50h) ...................................................................................14

CFI Query (98h) ..................................................................................................................15

Word Program (40h/10h) ....................................................................................................15

3.5.1 Suspending and Resuming Program (B0h/D0h)....................................................15

Block Erase (20h) ...............................................................................................................16

3.6.1 Suspending and Resuming Erase (B0h/D0h) ........................................................16

Block Locking......................................................................................................................18

3.7.1 Block Locking Operation Summary........................................................................19

3.7.2 Locked State ..........................................................................................................19

3.7.3 Unlocked State ......................................................................................................19

3.7.4 Lock-Down State ...................................................................................................19

3.7.5 Reading a Block’s Lock Status ..............................................................................20

3.7.6 Locking Operation during Erase Suspend .............................................................20

3.7.7 Status Register Error Checking .............................................................................20

128 Bit Protection Register .................................................................................................21

3.8.1 Reading the Protection Register ............................................................................21

3.8.2 Programming the Protection Register (C0h)..........................................................21

3.8.3 Locking the Protection Register .............................................................................22

Power-Up/Down Characteristics.........................................................................................23

Additional Flash Features ...................................................................................................23

4.2.1 Improved 12 Volt Production Programming ...........................................................23

4.2.2 F-VPP < VPPLK for Complete Protection..............................................................23

Absolute Maximum Ratings ................................................................................................24

Operating Conditions ..........................................................................................................25

Capacitance ........................................................................................................................25

Principles of Operation

...............................................................................................................11

3.0

Flash Memory Modes of Operation............................................................................................13

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

4.0

Power and Reset Considerations

..............................................................................................23

4.1

4.2

5.0

Electrical Specifications

.............................................................................................................24

5.1

5.2

5.3

Datasheet

Contents

5.4

5.5

5.6

5.7

5.8

5.9

5.10

5.11

6.0

7.0

DC Characteristics.............................................................................................................. 26

Flash AC Characteristics. ................................................................................................... 29

Flash AC Characteristics—Write Operations...................................................................... 31

Flash Erase and Program Timings(1)................................................................................. 31

Flash Reset Operations ...................................................................................................... 34

SRAM AC Characteristics—Read Operations.................................................................... 35

SRAM AC Characteristics—Write Operations .................................................................... 37

SRAM Data Retention Characteristics—Extended Temperature ....................................... 39

Migration Guide Information

...................................................................................................... 40

System Design Considerations..................................................................................................

7.1

Background......................................................................................................................... 41

7.1.1 Flash + SRAM Footprint Integration ...................................................................... 41

7.1.2 Advanced+ Boot Block Flash Memory Features ................................................... 41

Flash Control Considerations ............................................................................................. 41

7.2.1 F-RP# Connected to System Reset....................................................................... 42

7.2.2 F-VCC, F-VPP and F-RP# Transition .................................................................... 42

Noise Reduction ................................................................................................................. 43

Simultaneous Operation ..................................................................................................... 44

7.4.1 SRAM Operation during Flash “Busy” ................................................................... 45

7.4.2 Simultaneous Bus Operations ............................................................................... 45

Printed Circuit Board Notes ................................................................................................ 45

System Design Notes Summary......................................................................................... 45

7.2

7.3

7.4

7.5

7.6

Appendix A Program/Erase Flowcharts

............................................................................................. 46

Appendix B CFI Query Structure

........................................................................................................ 52

Appendix C Word-Wide Memory Map Diagrams

............................................................................... 59

Appendix D Device ID Table

................................................................................................................ 62

Appendix E Protection Register Addressing.....................................................................................

Appendix F Mechanical and Shipping Media Details........................................................................

Appendix G Additional Information

.................................................................................................... 68

Appendix H Ordering Information.......................................................................................................

Datasheet

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