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532VB10M000DG

Description
Oscillator
CategoryPassive components    oscillator   
File Size230KB,12 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

532VB10M000DG Overview

Oscillator

532VB10M000DG Parametric

Parameter NameAttribute value
Objectid110362128
Reach Compliance Codeunknown
Si532
R
EVISION
D
D
U A L
F
R E Q U E N C Y
C
R Y S TA L
O
S C I L L A T O R
(XO )
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
FS
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low jitter clock at high frequencies. The Si532 is
available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si532 uses one fixed crystal
frequency to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The Si532 IC
based XO is factory configurable for a wide variety of user specifications
including frequency, supply voltage, output format, and temperature stability.
Specific configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
CLK–
CLK+
(LVDS/LVPECL/CML)
FS
OE
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
(CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
FS
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si532
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