S29PL127J80BAW012 datasheet, PDF

Datasheet> All Categories > storage> storage> S29PL127J80BAW012

S29PL127J80BAW012: DescriptionFlash, 8MX16, 80ns, PBGA80, FBGA-80; Categorystorage storage; File Size8MB，101 Pages; ManufacturerCypress Semiconductor

Download Datasheet Parametric View All

S29PL127J80BAW012 Overview

Flash, 8MX16, 80ns, PBGA80, FBGA-80

S29PL127J80BAW012 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	8004818391
package instruction	FBGA-80
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	80 ns
Other features	TOP AND BOTTOM BOOT BLOCK
startup block	BOTTOM/TOP
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B80
length	11 mm
memory density	134217728 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	16,254
Number of terminals	80
word count	8388608 words
character code	8000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	8MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA80,8X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
page size	8 words
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1 mm
Department size	4K,32K
Maximum standby current	0.000005 A
Maximum slew rate	0.07 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
switch bit	YES
type	NOR TYPE
width	8 mm

Preview

Download Datasheet

View All

S29PL-J

128-/128-/64-/32-Mbit (8/8/4/2M x 16-Bit)

3V, Flash with Enhanced VersatileIO™

Distinctive Characteristics

Architectural Advantages



128-/128-/64-/32-Mbit Page Mode devices

– Page size of 8 words: Fast page read access from random

locations within the page



Single power supply operation

– Full Voltage range: 2.7 to 3.6 V read, erase, and program

operations for battery-powered applications



Dual Chip Enable inputs (only in PL129J)

– Two CE# inputs control selection of each half of the

memory space



Simultaneous Read/Write Operation

– Data can be continuously read from one bank while

executing erase/program functions in another bank

– Zero latency switching from write to read operations



FlexBank Architecture (PL127J/PL064J/PL032J)

– 4 separate banks, with up to two simultaneous operations

per device

– Bank A:

PL127J -16 Mbit (4 Kw



8 and 32 Kw



31)

PL064J - 8 Mbit (4 Kw



8 and 32 Kw



15)

PL032J - 4 Mbit (4 Kw



8 and 32 Kw



– Bank B:

PL127J - 48 Mbit (32 Kw



96)

PL064J - 24 Mbit (32 Kw



48)

PL032J - 12 Mbit (32 Kw



24)

– Bank C:

PL127J - 48 Mbit (32 Kw



96)

PL064J - 24 Mbit (32 Kw



48)

PL032J - 12 Mbit (32 Kw



24)

– Bank D:

PL127J -16 Mbit (4 Kw



8 and 32 Kw



31)

PL064J - 8 Mbit (4 Kw



8 and 32 Kw



15)

PL032J - 4 Mbit (4 Kw



8 and 32 Kw





FlexBank Architecture (PL129J)

– 4 separate banks, with up to two simultaneous operations

per device

– CE#1 controlled banks:

Bank 1A: PL129J - 16-Mbit (4Kw



8 and 32Kw



31)

Bank 1B: PL129J - 48-Mbit (32Kw



96)

– CE#2 controlled banks:

Bank 2A: PL129J - 48-Mbit (32 Kw



96)

Bank 2B: PL129J - 16-Mbit (4 Kw



8 and 32 Kw



31)



Enhanced VersatileI/O (V

) Control

– Output voltage generated and input voltages tolerated on

all control inputs and I/Os is determined by the voltage on

the V

– V

options at 1.8 V and 3 V I/O for PL127J and PL129J

devices

– 3V V

for PL064J and PL032J devices

Secured Silicon Sector region

– Up to 128 words accessible through a command sequence

– Up to 64 factory-locked words

– Up to 64 customer-lockable words

Both top and bottom boot blocks in one device

Manufactured on 110-nm process technology

Data Retention: 20 years typical

Cycling Endurance: 1 million cycles per sector typical



Performance Characteristics



High Performance

– Page access times as fast as 20 ns

– Random access times as fast as 55 ns



Power consumption (typical values at 10 MHz)

– 45 mA active read current

– 17 mA program/erase current

– 0.2

A

typical standby mode current

Software Features



Software command-set compatible with JEDEC 42.4

standard

– Backward compatible with Am29F, Am29LV, Am29DL, and

AM29PDL families and MBM29QM/RM, MBM29LV,

MBM29DL, MBM29PDL families



CFI (Common Flash Interface) compliant

– Provides device-specific information to the system,

allowing host software to easily reconfigure for different

Flash devices



Erase Suspend / Erase Resume

– Suspends an erase operation to allow read or program

operations in other sectors of same bank



Program Suspend / Program Resume

– Suspends a program operation to allow read operation

from sectors other than the one being programmed



Unlock Bypass Program command



Reduces overall programming time when issuing multiple

program command sequences

Cypress Semiconductor Corporation

Document Number: 002-00615 Rev. *B

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised August 10, 2016

S29PL-J

2.1

Page Mode Features

The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of

random locations within that page.

2.2

Standard Flash Memory Features

The device requires a

single 3.0 volt power supply

(2.7 V to 3.6 V) for both read and write functions. Internally generated and

regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash standard.

Commands are written

to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine

that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming

and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster

programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase

command sequence.

The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle)

status bits.

After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other

sectors. The device is fully erased when shipped from the factory.

Hardware data protection

measures include a low V

detector that automatically inhibits write operations during power

transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of

memory. This can be achieved in-system or via programming equipment.

The Erase Suspend/Erase Resume

feature enables the user to put erase on hold for any period of time to read data from, or

program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from

the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command

sequence to enter and exit this region.

The

Program Suspend/Program Resume

feature enables the user to hold the program operation to read data from any sector that

is not selected for programming. If a read is needed from the Secured Silicon Sector area, Persistent Protection area, Dynamic

Protection area, or the CFI area, after a program suspend, then the user must use the proper command sequence to enter and exit

this region.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters

the

automatic sleep mode.

The system can also place the device into the standby mode. Power consumption is greatly reduced in

both these modes. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

Document Number: 002-00615 Rev. *B

Page 5 of 101

Recommended Resources

Resistance Multiplier Circuit Diagram

Application of Huifeng inverter in central air conditioning control

Rongsheng CFXB-2 single-lamp thermal insulation automatic rice cooker circuit diagram

Full-duplex optical RS-232 connector

555 timer circuit with adjustable intermittent time

Three capacitor braking circuit

Embedded Qt-Simple Network Surveillance Camera: This article uses Qt to implement a network camera function, which includes a server and a client. The server is used to convert the USB camera into an IP camera. When a client is connected, the captu...; DDZZ669 ARM Technology

The connection and difference between inductors and magnetic beads: What is the connection and difference between inductors and magnetic beads?1. Inductors are energy storage components, while magnetic beads are energy conversion (consumption) devices.2. Inductors are...; murata888 Energy Infrastructure?

No results for complex SQL CE 3.0 queries on WinCE 6: The source program is for Windows Mobile and runs fine. Now I want to port it to WinCE 6 and there is a problem. Simple queries are fine on WinCE 6, but more complex queries, such as multi-table join ...; yucaic Embedded System

Can miniusb be used?: A: Can the miniUSB on the development board be used? Why can't the computer recognize this miniusb? B: Burn mode, plug in the mini USB cable and power onThe programming mode must be set correctly A: O...; 明远智睿Lan Talking

Harbin Institute of Technology training on the application of various simulation software: [i=s]This post was last edited by paulhyde on 2014-9-15 04:24[/i] Although the information is a bit brief, it is absolutely classic. I listened to the teacher's lecture for a day and benefited a lot....; sl1990925 Electronics Design Contest

ADS compilation interrupt function problem: ADS compilation problem: I defined an interrupt function void __irq time0Up(void); The interrupt function is as follows: void __irq time0Up(void) { int i=1; i=i+1; } The compilation error is as follow...; hargendazs Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components