ICS511
LOCO
TM
PLL C
LOCK
M
ULTIPLIER
Description
The ICS511 LOCO
TM
is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to 200
MHz.
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
The device also has an output enable pin which
tri-states the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
Features
•
Packaged as 8-pin SOIC or die
•
Available in Pb (lead) free package
•
Upgrade of popular ICS501 with:
- changed multiplier table
- faster operating frequencies
- output duty cycle at VDD/2
Zero ppm multiplication error
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 200 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 200 MHz
Mask option for nine selectable frequencies
Operating voltage of 3.3 V or 5 V
Tri-state output for board level testing
Industrial temperature version available
Advanced, low power CMOS process
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Block Diagram
VDD
S1:0
X1/ICLK
Crystal or
Clock input
X2
2
Crystal
Oscillator
PLL Clock
Multiplier
Circuitry
and ROM
CLK
Optional crystal capacitors
GND
OE
MDS 511 G
I n t e gra te d C i r c u i t S y s t e m s
●
1
5 25 Race Stre et, San Jo se, CA 9 5126
●
Revision 102504
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
ICS511
LOCO
TM
PLL Clock Multiplier
Pin Assignment
Clock Output Table
S1
S0
CLK
0
X1/ I CLK
VDD
GND
S1
1
2
3
4
8
7
6
5
X2
OE
S0
CLK
0
0
M
M
M
8 Pi n ( 150 mi l ) SOI C
1
1
1
0
M
1
0
M
1
0
M
1
4X input
5.333X input
5X input
2.5X input
2X input
3.333X input
6X input
3X input
8X input
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output
Input
Selection (S1, S0)
Output
Input
Selection (S1, S0)
20
24
30
32
33.33
37.5
40
48
50
60
64
10
M, M
66.66
12
M, M
72
10
1, M
75
16
M, M
80
16.66
M, M
83.33
15
M, 0
90
10
0, 0
100
12
0, 0
120
20
M, 0
125
10
1, 0
133.3
16
0, 0
150
20
M, 1
12
1, 0
25
1, M
10
1, 1
25
M, 1
15
1, 0
20
0, 1
15
1, 1
25
0, 1
25
0, M
25
1, 0
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
XI/ICLK
VDD
GND
S1
CLK
S0
OE
X2
Pin
Type
Input
Power
Power
Tri-level Iinput
Output
Tri-level Input
Input
Output
Pin Description
Crystal connection or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Select 1 for output clock. Connect to GND or VDD or float.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float.
Output enable. Tri-states CLK output when low. Internal pull-up
resistor.
Crystal connection. Leave unconnected for clock input.
MDS 511 G
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 102504
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m
ICS511
LOCO
TM
PLL Clock Multiplier
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS511 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected
close to the ICS511 to minimize lead inductance. No
external power supply filtering is required for the
ICS511.
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-12 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the CLK
pin for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS511. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (Commercial grade)
Ambient Operating Temperature (Industrial grade)
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70°C
-40 to +85°C
-65 to +150°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.135
Typ.
Max.
+85
+5.25
Units
°C
V
MDS 511 G
In te grat ed Circuit Syst ems
●
3
525 Ra ce St reet , San Jose, CA 9512 6
●
Revision 102504
t el (4 08) 297 -1 201
●
w w w. i c s t . c o m
ICS511
LOCO
TM
PLL Clock Multiplier
DC Electrical Characteristics
VDD=3.3 V ±5%
, Ambient temperature -40 to +85°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
IDD Operating Supply Current,
20 MHz crystal
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance, S1, S0, and OE
Nominal Output Impedance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Conditions
ICLK (pin 1)
ICLK (pin 1)
OE (pin 7)
OE (pin 7)
S0, S1
S0, S1
I
OH
= -25 mA
I
OL
= 25 mA
No load, 100M
CLK output
Pin 7
Pins 4, 6, 7
Min.
3.135
(VDD/2)+0.7
Typ.
Max.
3.465
(VDD/2)-0.7
Units
V
V
V
V
V
V
V
V
V
mA
mA
kΩ
pF
Ω
2.0
0.8
VDD-0.5
0.5
2.4
0.4
8
+70
270
4
20
AC Electrical Characteristics
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
PLL Bandwidth
Output Enable Time, OE high to
output on
Output Disable Time, OE low to
tri-state
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Symbol
F
IN
F
IN
F
OUT
t
OR
t
OF
t
OD
Conditions
Min.
5
2
Typ.
Max.
27
50
160
145
Units
MHz
MHz
MHz
MHz
ns
ns
0°C to +70°C
-40°C to +85°C
0.8 to 2.0 V, Note 1
2.0 to 8.0 V, Note 1
1.5 V, up to 160 MHz
14
14
1
1
45
10
50
50
49-51
55
%
kHz
ns
ns
ps
ps
t
ja
t
js
Deviation from mean
+70
25
Note 1: Measured with 15 pF load.
MDS 511 G
In te grat ed Circuit Syst ems
●
4
525 Ra ce St reet , San Jose, CA 9512 6
●
Revision 102504
t el (4 08) 297 -1 201
●
w w w. i c s t . c o m
ICS511
LOCO
TM
PLL Clock Multiplier
DC Electrical Characteristics
VDD=5.0 V ±5%
, Ambient temperature -40 to +85°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
IDD Operating Supply Current,
20 MHz crystal
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance, S1, S0, and OE
Nominal Output Impedance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Conditions
ICLK (pin 1)
ICLK (pin 1)
OE (pin 7)
OE (pin 7)
S0, S1
S0, S1
I
OH
= -25 mA
I
OL
= 25 mA
No load, 100M
CLK output
Pin 7
Pins 4, 6, 7
Min.
4.75
(VDD/2)+1
Typ.
Max.
5.25
(VDD/2)-1
Units
V
V
V
V
V
V
V
V
V
mA
mA
kΩ
pF
Ω
2.0
0.8
VDD-0.5
0.5
2.4
0.4
9
+70
270
4
20
AC Electrical Characteristics
VDD = 5.0 V ±5%,
Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
PLL Bandwidth
Output Enable Time, OE high to
output on
Output Disable Time, OE low to
tri-state
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Symbol
F
IN
F
IN
F
OUT
t
OR
t
OF
t
OD
Conditions
Min.
5
2
Typ.
Max.
27
50
200
160
Units
MHz
MHz
MHz
MHz
ns
ns
0°C to +70°C
-40°C to +85°C
0.8 to 2.0 V, Note 1
2.0 to 8.0 V, Note 1
1.5 V, up to 160 MHz
14
14
1
1
45
10
50
50
49-51
55
%
kHz
ns
ns
ps
ps
t
ja
t
js
Deviation from mean
+70
25
Note 1: Measured with 15 pF load.
MDS 511 G
In te grat ed Circuit Syst ems
●
5
525 Ra ce St reet , San Jose, CA 9512 6
●
Revision 102504
t el (4 08) 297 -1 201
●
w w w. i c s t . c o m
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