DSPIC33CK256MP202T-E/2N datasheet, PDF

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DSPIC33CK256MP202T-E/2N: DescriptionDigital Signal Processor, 0-Ext Bit, 64MHz, CMOS, PQCC28; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，640 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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DSPIC33CK256MP202T-E/2N Overview

Digital Signal Processor, 0-Ext Bit, 64MHz, CMOS, PQCC28

DSPIC33CK256MP202T-E/2N Parametric

Parameter Name	Attribute value
Objectid	7372043850
package instruction	HVQCCN, LCC28,24SQ,20
Reach Compliance Code	compliant
Country Of Origin	Thailand
ECCN code	3A001.A.3
YTEOL	6.5
Address bus width
barrel shifter	YES
bit size	16
boundary scan	YES
maximum clock frequency	64 MHz
External data bus width
Format	FIXED POINT
Integrated cache	NO
Internal bus architecture	MULTIPLE
JESD-30 code	S-PQCC-N28
length	6 mm
low power mode	YES
Number of DMA channels	4
Number of external interrupt devices	4
Number of terminals	28
Number of timers	11
On-chip data RAM width	8
On-chip program ROM width	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC28,.24SQ,25
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
RAM (number of words)	24576
ROM programmability	FLASH
Filter level	AEC-Q100
Maximum seat height	0.55 mm
Maximum slew rate	300 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	NO LEAD
Terminal pitch	0.65 mm
Terminal location	QUAD
width	6 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, CONTROLLER

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dsPIC33CK256MP508 FAMILY

28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers

with High-Resolution PWM and CAN Flexible Data (CAN FD)

Operating Conditions

• 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS

• 3.0V to 3.6V, -40°C to +150°C, DC to 70 MIPS

Power Management

• Low-Power Management Modes (Sleep,

Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

Core: 16-Bit dsPIC33CK CPU

• 32-256 Kbytes of Program Flash with ECC and

8-24K RAM

• Fast 6-Cycle Divide

• LiveUpdate

• Code Efficient (C and Assembly) Architecture

• 40-Bit Wide Accumulators

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle, Mixed-Sign MUL Plus

Hardware Divide

• 32-Bit Multiply Support

• Four Sets of Interrupt Context Saving Registers

which Include Accumulator and STATUS for Fast

Interrupt Handling

• Zero Overhead Looping

• RAM Memory Built-In Self-Test (MBIST)

High-Speed PWM

•

8 PWM Pairs

Up to 250 ps PWM Resolution

Dead Time for Rising and Falling Edges

Dead-Time Compensation

Clock Chopping for High-Frequency Operation

PWM Support for:

- DC/DC, AC/DC, inverters, PFC, lighting

- BLDC, PMSM, ACIM, SRM motors

• Fault and Current Limit Inputs

• Flexible Trigger Configuration for ADC Triggering

Timers/Output Compare/Input Capture

• One General Purpose Timer

• Peripheral Trigger Generator (PTG):

- Up to 15 trigger sources to other

peripheral modules

- CPU independent state machine-based

instruction sequencer

• Nine MCCP/SCCP modules which Include Timer,

Capture/Compare and PWM:

- 1 MCCP

- 8 SCCPs

- 16 or 32-bit time base

- 16 or 32-bit capture

- 4-deep capture buffer

• Fully Asynchronous Operation, Available in

Sleep Modes

Clock Management

•

Internal Oscillator

Programmable PLLs and Oscillator Clock Sources

Reference Clock Output

Fail-Safe Clock Monitor (FSCM)

Fast Wake-up and Start-up

Backup Internal Oscillator



2017-2020 Microchip Technology Inc.

DS70005349H-page 1

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