PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS854058
8:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
F
EATURES
•
High speed 8:1 differential multiplexer
•
1 differential LVDS output
•
8 selectable differential PCLK, nPCLK inputs
•
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: 2.5GHz
•
Translates any single ended input signal to
LVDS levels with resistor bias on nPCLKx input
•
Part-to-part skew: TBD
•
Propagation delay: 595ps (typical)
•
Supply voltage range: 3.135V to 3.465V
•
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS854058 is an 8:1 Differential-to-LVDS Clock
Multiplexer which can operate up to 2.5GHz and
HiPerClockS™
is a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS854058 has 8 selectable differential clock in-
puts. The PCLK, nPCLK input pairs can accept LVPECL, LVDS,
CML or SSTL levels. The fully differential architecture and low
propagation delay make it ideal for use in clock distribution cir-
cuits. The select pins have internal pulldown resistors. The SEL2
pin is the most significant bit and the binary number applied to
the select pins will select the same numbered data input (i.e.,
000 selects PCLK0, nPCLK0).
ICS
B
LOCK
D
IAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
PCLK4
nPCLK4
PCLK5
nPCLK5
PCLK6
nPCLK6
PCLK7
nPCLK7
P
IN
A
SSIGNMENT
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
Q0
nQ0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
000
001
010
011
PCLK7
nPCLK7
PLCK6
nPCLK6
V
DD
Q0
nQ0
GND
PCLK5
nPCLK5
PCLK4
nPCLK4
100
ICS854058
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
101
110
111
SEL2
SEL1 SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
854058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 8, 2004
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS854058
8:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
Type
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Input
Input
Input
Input
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Description
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
DD
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
DD
/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
DD
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
DD
/2 default when left floating.
Inver ting differential LVPECL clock input.
V
DD
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
DD
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Power supply ground.
Differential output pair. LVDS interface levels.
Inver ting differential LVPECL clock input.
V
DD
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
V
DD
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5, 20
6, 7, 8
9
10
11
12
13
14
15
16
17
18, 19
21
22
23
24
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0, SEL1, SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nPCLK4
PCLK4
nPCLK5
PCLK5
GND
nQ0, Q0
nP CLK 6
PCLK6
nPCLK7
PCLK7
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
854058AG
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 8, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS854058
8:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
Test Conditions
Minimum Typical
75
50
Maximum
Units
KΩ
KΩ
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VDD/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL2
0
0
0
0
1
1
1
1
S E L1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Q0
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
Outputs
nQ0
nPCLK0
nPCLK1
nPCLK2
nPCLK3
nPCLK4
nPCLK5
nPCLK6
nPCLK7
854058AG
www.icst.com/products/hiperclocks.html
3
REV. A APRIL 8, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS854058
8:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
68
Maximum
3.465
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input High Current
Input Low Current
SEL0:SEL2
SEL0:SEL2
SEL0:SEL2
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-10
Input Low Voltage SEL0:SEL2
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%
Symbol Parameter
I
IH
I
IL
V
PP
Input High Current
Input Low Current
PCLK0:PCLK7
nPCLK0:nPCLK7
PCLK0:PCLK7
nPCLK0:nPCLK7
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-10
-150
0.15
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is V
DD
+ 0.3V.
854058AG
www.icst.com/products/hiperclocks.html
4
REV. A APRIL 8, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS854058
8:1
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
M
ULTIPLEXER
Test Conditions
Minimum
Typical
350
50
1.25
50
Maximum
Units
mV
mV
V
mV
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%
Symbol
V
OD
∆
V
OD
V
OS
∆
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.135V
TO
3.465V
Symbol Parameter
f
MAX
t
PD
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
595
TBD
Test Conditions
Minimum
Typical
Maximum
2.5
Units
GHz
ps
ps
ps
t
sk(pp)
Output Rise/Fall Time
20% to 80%
180
t
R
/ t
F
All parameters measured up to 1.3GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
854058AG
www.icst.com/products/hiperclocks.html
5
REV. A APRIL 8, 2004
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