Integrated
Circuit
Systems, Inc.
ICS87004
1:4, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
EATURES
• 4 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Internal bias on nCLK0 and nCLK1 to support
LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 45ps (maximum)
• Static phase offset: 50 ± 125ps (3.3V ± 5%)
• Full 3.3V or 2.5V operating supply
• 5V tolerant inputs
• Lead-Free package available
• Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS87004 is a highly versatile 1:4 Differential-
to-LVCMOS/LVTTL Clock Generator and a mem-
HiPerClockS™
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The ICS87004
has two selectable clock inputs. The CLK0, nCLK0
and CLK1, nCLK1 pairs can accept most standard differential
input levels. Internal bias on the nCLK0 and nCLK1 inputs
allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL.
The ICS87004 has a fully integrated PLL and can be configured
as zero delay buffer, multiplier or divider and has an input and
output frequency range of 15.625MHz to 250MHz. The refer-
ence divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-
input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The exter-
nal feedback allows the device to achieve “zero delay” between
the input clock and the output clocks. The PLL_SEL pin can be
used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
ICS
B
LOCK
D
IAGRAM
PLL_SEL
÷2, ÷4, ÷8, ÷16,
÷32
,
÷64, ÷128
0
P
IN
A
SSIGNMENT
Q0
0
GND
Q0
V
DD
o
SEL0
SEL1
SEL2
SEL3
CLK_SEL
V
DD
CLK0
nCLK0
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q1
V
DDO
Q2
GND
Q3
V
DDO
MR
FB_IN
PLL_SEL
CLK1
nCLK1
V
DDA
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
Q1
1
1
PLL
Q2
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q3
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
G Package
Top View
SEL0
SEL1
SEL2
SEL3
MR
87004AG
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 16, 2004
Integrated
Circuit
Systems, Inc.
ICS87004
1:4, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Type
Power
Output
Power
Input
Input
Power
Input
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 12, 21
2, 20, 22, 24
3, 19, 23
4, 5, 6, 7
8
9
10
Name
GND
Q0, Q3,
Q2, Q1
V
DDO
SEL0, SEL1,
SEL2, SEL3
CLK_SEL
V
DD
CLK0
Power supply ground.
Clock outputs. 7
Ω
typical output impedance.
LVCMOS/LVTTL interface levels.
Output supply pins.
Determines output divider values in Table 3.
Pulldown
LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects differential CLK1, nCLK1.
Pulldown When LOW, selects differential CLK0, nCLK0.
LVCMOS/LVTTL interface levels.
Core supply pin.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
11
nCLK0
Input
Pulldown
13
V
DDA
Power
Analog supply pin.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
14
nCLK1
Input
Pulldown
15
CLK1
Input
Pulldown Non-inver ting differential clock input.
Selects between the PLL and reference clock as input to the dividers.
16
PLL_SEL
Input
Pullup
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL feedback input to phase detector for regenerating
17
FB_IN
Input
Pulldown clocks with "zero delay". Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
18
MR
Input
Pulldown reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
V
DD
, V
DDA
, V
DDO
= 3.465V
V
DD
, V
DDA
, V
DDO
= 2.625V
5
7
Test Conditions
Minimum
Typical
4
51
51
23
17
12
Maximum
Units
pF
KΩ
KΩ
pF
pF
Ω
87004AG
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 16, 2004
Integrated
Circuit
Systems, Inc.
ICS87004
1:4, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q3
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
T
ABLE
3A. PLL E
NABLE
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S E L0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Frequency Range (MHz)
125 - 250
62.5 - 125
31.25 - 62.5
15.625 -31.25
125 - 250
62.5 - 125
31.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
31.25 - 62.5
15.625 - 31.25
15.625 - 31.25
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
87004AG
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S E L1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S E L0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q3
÷8
÷8
÷8
÷ 16
÷ 16
÷ 16
÷ 32
÷ 32
÷ 64
÷ 128
÷4
÷4
÷8
÷2
÷4
÷2
REV. A JUNE 16, 2004
www.icst.com/products/hiperclocks.html
3
Integrated
Circuit
Systems, Inc.
ICS87004
1:4, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
100
16
6
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%
OR
2.5V±5%, TA = 0°C
TO
70°C
Symbol
V
IH
Parameter
Input
High Voltage
Input
Low Voltage
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
CLK_SEL, MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
PLL_SEL
CLK_SEL, MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
PLL_SEL
V
DD
= V
IN
= 3.465V,
V
DD
= V
IN
= 2.625V
V
DD
= V
IN
= 3.465V,
V
DD
= V
IN
= 2.625V
V
DD
= 3.465V, V
IN
= 0V,
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V,
V
DD
= 2.625V, V
IN
= 0V
V
DDO
= 3.465V
V
DDO
= 2.625V
-5
-150
2.6
1.8
0.5
Test Conditions
Minimum Typical
2
Maximum
V
DD
+ 0.3
Units
V
V
IL
-0.3
0.8
150
5
V
µA
µA
µA
µA
V
V
V
I
IH
Input
High Current
I
IL
Input
Low Current
V
OH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DDO
= 3.465V or 2.625V
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. In the Parameter Measurement Information Section,
see
Output Load Test Circuit Diagrams.
87004AG
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 16, 2004
Integrated
Circuit
Systems, Inc.
ICS87004
1:4, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Test Conditions
CLK0, CLK1
V
DD
= V
IN
= 3.465V,
V
DD
= V
IN
= 2.625V
V
DD
= V
IN
= 3.465V,
V
DD
= V
IN
= 2.625V
V
DD
= 3.465V, V
IN
= 0V,
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V,
V
DD
= 2.625V, V
IN
= 0V
-5
-150
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%
OR
2.5V±5%, TA = 0°C
TO
70°C
Symbol Parameter
I
IH
Input High Current
nCLK0, nCLK1
CLK0, CLK1
I
IL
Input Low Current
nCLK0, nCLK1
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
GND + 0.5
V
DD
- 0.85
V
CMR
NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is V
DD
+ 0.3V.
V
PP
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
96
15
6
Units
V
V
V
mA
mA
mA
87004AG
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 16, 2004
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