Integrated
Circuit
Systems, Inc.
ICS91718
Low EMI, Spread Modulating, Clock Generator
Features:
•
ICS91718 is a Spread Spectrum Clock targeted
for Mobile PC and LCD panel applications.
Generates an EMI optimized clock signal (EMI
peak reduction of 7-14 dB on 3rd-19th harmonics)
through use of Spread Spectrum techniques.
•
ICS91718 operates with input frequencies at
14.318 - 80 MHz.
•
Spread modulation frequency range is 20kHz to
40kHz.
•
Spread percentage/type programming through
I
2
C.
Specifications:
•
Supply Voltages: V
DD
= 3.3V ±0.3V
•
Cyc to Cyc jitter: <150ps
•
Output duty cycle 45/55%
•
Guarantees +85°C operational condition
•
8-pin SOIC (150 mil) package
Pin Configuration
CLKIN
VDD
GND
**
CLKOUT/FS_IN0
1
2
3
4
8
7
6
5
PD#
*
SCLK
SDATA
REF_OUT/FS_IN1
**
8-pin SOIC & TSSOP
Notes:
* Internal pull-up resistor
** Internal pull-down resistor
Input Select Functionality
FS_IN1 FS_IN0
0
0
1
1
0
1
0
1
MHz
14.318 in
48.00 out
14.318 in
66.66 out
48.00 in/out
66.66 in/out
48.00 in/out
66.66 in/out
SPREAD %
-1.0% down sprd
-1.0% down sprd
-1.0% down sprd
+/-1.0% center sprd
Block Diagram
REFOUT
CLKIN
PLL1
Spread
Spectrum
Spectrum
CLKOUT
CLKOUT
PD#
FS_IN0:1
SDATA
SD
SCLK
Control
Logic
Config.
Reg.
0500D—07/15/04
ICS91718
Pin Descriptions
PIN
#
1
2
3
4
5
6
7
8
PIN NAME
CLKIN
VDD
GND
**CLKOUT/FS_IN0
REF_OUT/FS_IN1**
SDATA
SCLK
PD#*
PIN
DESCRIPTION
TYPE
IN
Input clock
PWR Power supply, nominal 3.3V
PWR Ground pin.
CLKOUT modulated clock output
I/O
FS_IN0 latched input, selects modulation percentage/type
REF_OUT, unmodulated reference clock output
I/O
FS_IN1 latched input, selects modulation percentage/type
I/O Data pin for I2C circuitry 5V tolerant
IN
Clock pin of I2C circuitry 5V tolerant
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
IN
crystal are stopped. The latency of the power down will not be greater
than 1.8ms.
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0500D—07/15/04
2
ICS91718
Table 1: Frequency Configuration Table
(See I2C Byte 0)
FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd %
0
0
0
0
0
0.80
0
0
0
0
1
1.00
DOWN
0
0
0
1
0
1.25
SPREAD
0
0
0
1
1
1.50
(-)
0
0
1
0
0
1.75
0
0
1
0
1
2.00
0
0
1
1
0
2.50
0
0
1
1
1
0.60
CENTER
0
1
0
0
0
1.00
SPREAD
0
1
0
0
1
1.25
(+/-)
0
1
0
1
0
1.50
0
1
0
1
1
2.00
0
1
1
0
0
1.25
DOWN
0
1
1
0
1
1.00
SPREAD
0
1
1
1
0
1.50
(-)
0
1
1
1
1
2.00
1
0
0
0
0
0.80
1
0
0
0
1
1.00
1
0
0
1
0
1.25
DOWN
1
0
0
1
1
1.50
SPREAD
1
0
1
0
0
1.75
(-)
1
0
1
0
1
2.00
1
0
1
1
0
2.50
1
0
1
1
1
3.00
1
1
0
0
0
0.30
1
1
0
0
1
0.40
1
1
0
1
0
0.50
CENTER
1
1
0
1
1
0.60
SPREAD
1
1
1
0
0
0.80
(+/-)
1
1
1
0
1
1.00
1
1
1
1
0
1.25
1
1
1
1
1
1.50
14in/48out
14in/66out
48in/48out
66in/66out
For 14.318 in 48.008 out default is…
..00001
For 14.318 in 66.66 out default is…
…
01101
For 48/48 and 66/66 default is… .10001
…
…
0500D—07/15/04
3
ICS91718
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will
acknowledge
each byte
one at a time
.
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Write:
Controller (Host)
Start Bit
Address
D4
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
ACK
Stop Bit
ICS (Slave/Receiver)
How to Read:
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D5
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 7
Controller (host) will need to acknowledge each
byte
• Controller (host) will send a stop bit
How to Read:
Controller (Host)
Start Bit
Address
D5
(H)
ICS (Slave/Receiver)
ACK
ACK
ACK
Byte Count
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
Stop Bit
Notes:
1. The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
0500D—07/15/04
4
ICS91718
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
Name
N/A
N/A
N/A
N/A
N/A
N/A
N/A
HW/SW Control
Control Function
FS0
FS1
FS2
FS3
FS4
PD# Tri_Sate
Spread Enable
Spread Spectrum Control
FS 2:4 Hard/Software
Select
TYPE
BYTE
Affected Pin
Bit Control
0
1
PWD
RW
RW
RW See ROM TABLE
RW
RW
RW
Hi-Z
LOW
RW
OFF
ON
RW
HW
SW
1
0
0
0
0
1
1
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BYTE
Pin #
5
5
Name
REF_OUT
REF_OUT
FS_IN1 Readback
FS_IN0 Readback
CLK_OUT
CLK_OUT
Reserved
Reserved
Control Function
REF_OUT ENABLE
Slew Rate REF-OUT
FS_IN1 Readback
FS_IN0 Readback
Slew Rate CLK-OUT
CLK_OUT_Enable
Reserved
Reserved
TYPE
BYTE
Affected Pin
Bit Control
0
1
PWD
4
4
RW
RW
RW
RW
RW
RW
R
R
TYPE
Disable Enable
Nominal Fast
-
-
-
-
Nominal Fast
Disable Enable
-
-
-
-
1
1
1
1
1
1
1
1
Affected Pin
Pin #
x
x
x
x
x
x
x
x
Bit Control
0
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
-
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
-
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
0500D—07/15/04
5
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