Integrated
Circuit
Systems, Inc.
ICS932S208
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409B clock, Intel Yellow Cover part, Server Applications
Output Features:
•
4 - 0.7V current-mode differential CPU pairs
•
1 - 0.7V current-mode differential SRC pair
•
7 - PCI (33MHz)
•
3 - PCICLK_F, (33MHz) free-running
•
1 - USB, 48MHz
•
1 - DOT, 48MHz
•
2 - REF, 14.318MHz
•
4 - 3V66, 66.66MHz
•
1 - VCH/3V66, selectable 48MHz or 66MHz
Key Specifications:
•
CPU/SRC outputs cycle-cycle jitter < 125ps
•
3V66 outputs cycle-cycle jitter < 250ps
•
PCI outputs cycle-cycle jitter < 250ps
•
CPU outputs skew: < 100ps
•
+/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA
•
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
•
•
Supports CPU clks up to 400MHz in test mode
Uses external 14.318MHz crystal
Pin Configuration
Functionality
CPU
B6b5 FS_A FS_B MHz
0
0
100
0
MID Ref/N
0
0
1
200
0
1
0
133
1
1
166
1
MID Hi-Z
0
0
200
0
1
400
1
1
0
266
1
1
333
SRC
MHz
100/200
Ref/N
1
100/200
100/200
100/200
Hi-Z
100/200
100/200
100/200
100/200
3V66
MHz
66.66
Ref/N
2
66.66
66.66
66.66
Hi-Z
66.66
66.66
66.66
66.66
PCI
MHz
33.33
Ref/N
3
33.33
33.33
33.33
Hi-Z
33.33
33.33
33.33
33.33
REF U
SB/DOT
MHz
MHz
14.318
48.00
Ref/N
4
Ref/N
5
14.318
48.00
14.318
48.00
14.318
48.00
Hi-Z
Hi-Z
14.318
48.00
14.318
48.00
14.318
48.00
14.318
48.00
REF0
REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
PD#
3V66_0
3V66_1
VDD3V66
GND
3V66_2
3V66_3
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_B
VDDA
GNDA
GND
IREF
FS_A
CPUCLKT3
CPUCLKC3
VDDCPU
CPUCLKT2
CPUCLKC2
GND
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GND
SRCCLKT
SRCCLKC
VDD
Vtt_PWRGD#
VDD48
GND
48MHz_DOT
48MHz_USB
SDATA
3V66_4/VCH
56-pin SSOP & TSSOP
0743D—07/07/04
ICS932S208
Integrated
Circuit
Systems, Inc.
ICS932S208
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
REF0
REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
PD#
3V66_0
3V66_1
VDD3V66
GND
3V66_2
3V66_3
SCLK
PIN TYPE
OUT
OUT
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
DESCRIPTION
14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 1.8ms. Internal pull-up of 150K nominal.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of I2C circuitry 5V tolerant
0743D—07/07/04
2
Integrated
Circuit
Systems, Inc.
ICS932S208
Pin Description (Continued)
PIN #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
PIN NAME
3V66_4/VCH
SDATA
48MHz_USB
48MHz_DOT
GND
VDD48
Vtt_PWRGD#
VDD
SRCCLKC
SRCCLKT
GND
CPUCLKC0
CPUCLKT0
VDDCPU
CPUCLKC1
CPUCLKT1
GND
CPUCLKC2
CPUCLKT2
VDDCPU
CPUCLKC3
CPUCLKT3
FS_A
IREF
GND
GNDA
VDDA
FS_B
PIN TYPE
OUT
I/O
OUT
OUT
PWR
PWR
IN
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
IN
OUT
PWR
PWR
PWR
IN
DESCRIPTION
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for I2C circuitry 5V tolerant
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Frequency select pin, see Frequency table for functionality
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
0743D—07/07/04
3
Integrated
Circuit
Systems, Inc.
ICS932S208
General Description
ICS932S208
follows Intel CK409B Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets.
ICS932S208
is driven with a 14.318MHz crystal. It generates CPU outputs
up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
PLL2
Frequency
Dividers
48MHz, USB, DOT
X1
X2
XTAL
REF (1:0)
CPUCLKT (3:0)
CPUCLKC (3:0)
SRCCLKT0
SCLK
SDATA
Vtt_PWRGD#
PD#
FS_A
FS_B
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
SRCCLKC0
3V66(4:0)
PCICLK (6:0)
PCICLKF (2:0)
I REF
Power Groups
Pin Number
VDD
GND
3
6
24
25
10,16
11,17
36
39
55
54
34
33
N/A
53
48, 42
45
Description
Xtal, Ref
3V66 [0:3]
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, PLL
IREF
CPUCLK clocks
0743D—07/07/04
4
Integrated
Circuit
Systems, Inc.
ICS932S208
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
Max
V
DD
+ 0.5V
V
DD
+ 0.5V
150
70
115
Units
V
V
°
C
°C
°C
V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
MID
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
1
3
CONDITIONS
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-up
resistors
V
IN
= 0 V; Inputs with pull-up
resistors
Full Active, C
L
= Full load;
all diff pairs driven
all differential pairs tri-stated
V
DD
= 3.3 V
MIN
2
1
V
SS
- 0.3
-5
-5
-200
TYP
MAX
UNITS NOTES
V
DD
+ 0.3
V
1.8
V
0.8
V
5
uA
uA
uA
350
35
12
mA
mA
mA
MHz
nH
pF
pF
pF
ms
kHz
ns
us
ns
ns
us
ns
ns
I
DD3.3OP
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
C
INX
14.31818
7
5
6
5
Logic Inputs
Output pin capacitance
Input Capacitance
X1 & X2 pins
From V
DD
Power-Up or de-
T
STAB
1.8
Clk Stabilization
1,2
assertion of PD# to 1st clock
Triangular Modulation
30
33
Modulation Frequency
SRC output enable after
15
Tdrive_SRC
PCI_Stop# de-assertion
CPU output enable after
Tdrive_PD#
300
PD# de-assertion
Tfall_Pd#
PD# fall time of
5
Trise_Pd#
PD# rise time of
5
CPU output enable after
Tdrive_CPU_Stop#
10
CPU_Stop# de-assertion
Tfall_CPU_Stop#
PD# fall time of
5
Trise_CPU_Stop#
PD# rise time of
5
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
1
3
1
1
1
1
1,2
1
1
1
1
2
1
1
2
0743D—07/07/04
5
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