Integrated
Circuit
Systems, Inc.
ICS93725
DDR and SDRAM Zero Delay Buffer
Recommended Application:
DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/
650 & 735/740/746 style chipsets.
Product Description/Features:
• Low skew, Zero Delay Buffer
• 1 to 13 SDRAM PC133 clock distribution
• 1 to 6 pairs of DDR clock distribution
• I
2
C for functional and output control
• Separate feedback path for both memory mode to
adjust synchronization.
• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs
• Frequency support for up to 200MHz
• Individual I
2
C clock stop for power mananagement
• CMOS level control signal input
Switching Characteristics:
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time for DDR outputs: 550ps -
1150ps
• DUTY CYCLE: 47% - 53%
Pin Configuration
VDD3.3
SDRAM0
SDRAM1
SDRAM2
SDRAM3
GND
VDD3.3
SDRAM4
SDRAM5
BUFFER_IN
SDRAM6
SDRAM7
GND
VDD3.3
SDRAM8
SDRAM9
SDRAM10
SDRAM11
GND
VDD3.3
SDRAM12
SDFB_OUT
SDFB_IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR*
DDRFB_IN
DDRFB_OUT
VDD2.5
DDRT5
DDRC5
DDRT4
DDRC4
GND
VDD2.5
DDRT3
DDRC3
DDRT2
DDRC2
GND
VDD2.5
DDRT1
DDRC1
DDRT0
DDRC0
GND
VDD2.5
SCLK
SDATA
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Block Diagram
SDRAMFB_OUT
PLL1
DDRFB_OUT
SDRAM (12:0)
Control
SEL_DDR*
SDATA
SCLK
Config.
Reg.
Logic
3
3
Functionality
MODE
PIN 48
SEL_DDR=1
SEL_DDR=0
VDD
3.3_2.5
2.5V
3.3V
BUFFER_IN
SDRAMFB_IN
DDRFB_IN
DDR
Mode
DDR/SD
Mode
DDRT (5:0)
DDRCC (5:0)
0606A—08/01/03
ICS93725
ICS93725
Pin Descriptions
PIN NUMBER
1, 7, 14, 20
6, 13, 19, 24, 34,
28, 40
44, 42, 38,
36, 32, 30
43, 41, 37,
35, 31, 29
PIN NAME
VDD3.3
GND
DDRT (5:0)
DDRC (5:0)
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
IN
OUT
IN
I/O
IN
OUT
IN
IN
DESCRIPTION
3.3V voltage supply for SDRAM.
Ground
"Tr ue" Clock of differential pair outputs.
"Complementor y" clocks of differential pair outputs.
SDRAM clock outputs
2.5V voltage supply for DDR.
Single ended buffer input
Feedback output for SDRAM
Feedback input for SDRAM
Data pin for I
2
C circuitr y 5V tolerant
Clock input of I
2
C input, 5V tolerant input
Feedback output for DDR
Feedback input for DDR
Select input for DDR mode or DDR/SD mode
0=SD mode 1=DDR mode
21, 18, 17, 16, 15,
12, 11, 9, 8, 5,
SDRAM (12:0)
4, 3, 2
27, 39, 45
10
22
23
25
26
46
47
48
VDD2.5
BUFFER_IN
SDRAMFB_OUT
SDFB_IN
SDATA
SCLK
DDRFB_OUT
DDRFB_IN
SEL_DDR
0606A—08/01/03
2
ICS93725
Byte 6: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
48
-
-
44, 43
42, 41
38, 37
36, 35
32, 31
PWD
-
1
1
1
1
1
1
1
DESCRIPTION
SEL_DDR (Read back only)
(Reserved)
(Reserved)
DDRT5, DDRC5
DDRT4, DDRC4
DDRT3, DDRC3
DDRT2, DDRC2
DDRT1, DDRC1
Byte 7: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
30, 29
21
17, 18
15, 16
11, 12
8, 9
4, 5
2, 3
PWD
DESCRIPTION
1 DDRT0, DDRC0
1
SDRAM12
SDRAM10
1
SDRAM11
SDRAM8
1
SDRAM9
SDRAM6
1
SDRAM7
SDRAM4
1
SDRAM5
SDRAM2
1
SDRAM3
SDRAM1
1
SDRAM0
0606A—08/01/03
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ICS93725
Absolute Maximum Ratings
Supply Voltage (VDD & VDD2.5) . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
-0.5V to 3.6V
GND –0.5 V to V
DD
+0.5 V
0°C to +85°C
115°C
–65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR=0 SDRAM Outputs V
DD
=3.3V,
T
A
=0 - 85°C; (unless otherwise stated)
PARAMETER
Operating Supply Current
Output High Current
Output Low Current
High-level output voltage
Low-level output voltage
SYMBOL
I
DD3.3
I
OH
I
OL
V
OH
V
OL
CONDITIONS
100MHz, RL=0Ω, CL = 0pF
133MHz, RL=0Ω, CL = 0pF
200MHz, RL=0Ω, CL = 0pF
V
DD
=3.3V, V
OUT
=1V
V
DD
=3.3V, V
OUT
=1.2V
V
DD
=3.3V
I
OH
= -12 mA
V
DD
=3.3V
I
OH
= 12 mA
V
I
= GND or V
DD
MIN
TYP
130
173
247
26
1.7
-40
34
2
0.4
2
0.6
-18
mA
mA
mA
mA
V
V
pF
MAX
UNITS
1
C
IN
Input Capacitance
1
Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=0 SDRAM Outputs V
DD
=3.3V,
T
A
=0 - 85°C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
V
DD3.3
3
Power Supply Voltage
V
IH
SEL_DDR, PD# input
2
Input High Voltage
V
IL
SEL_DDR, PD# input
Input Low Voltae
V
IN
Input Voltage Level
0
1
TYP
3.3
MAX
3.6
0.8
3.6
3.3
UNITS
V
V
V
V
Guaranteed by design, not 100% tested in production.
0606A—08/01/03
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ICS93725
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR=1 DDR Outputs V
DD
=2.5V,
T
A
=0 - 85°C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
100MHz, RL=0Ω, CL = 0pF
I
DD2.5
Operating Supply Current
133MHz, RL=0Ω, CL = 0pF
200MHz, RL=0Ω, CL = 0pF
V
DD
=2.5V, V
OUT
=1V
I
OH
Output High Current
V
DD
=2.5V, V
OUT
=1.2V
I
OL
Output Low Current
V
DD
=2.5V
V
OH
High-level output voltage
I
OH
= -12 mA
V
DD
=2.5V
V
OL
Low-level output voltage
I
OH
= 12 mA
V
DD
= 2.5V
Output differential-pair
V
OC
100/133/166/ 200 Mhz
Crossing voltage
1
C
IN
V
I
= GND or V
DD
Input Capacitance
1
MIN
26
1.7
TYP
141
188
271
-43
38
2
0.4
MAX
-18
UNITS
mA
mA
mA
mA
mA
V
0.6
1.45
V
V
pF
1.05
2
1.25
Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=1 DDR Outputs V
DD
=2.5V,
T
A
=0 - 85°C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
V
DD2.5
Power Supply Voltage
V
IH
SEL_DDR, PD# input
Input High Voltage
V
IL
SEL_DDR, PD# input
Input Low Voltage
V
IN
Input Voltage Level
1
MIN
2.3
2
0
TYP
2.5
MAX
2.7
0.8
2.7
2.5
UNITS
V
V
V
V
Guaranteed by design, not 100% tested in production.
0606A—08/01/03
5
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