EEWORLDEEWORLDEEWORLD

Part Number

Search

ICS950812

Description
Frequency Generator with 200MHz Differential CPU Clocks
File Size228KB,29 Pages
ManufacturerICS ( IDT )
Websitehttp://www.icst.com
Download Datasheet Compare View All

ICS950812 Overview

Frequency Generator with 200MHz Differential CPU Clocks

Integrated
Circuit
Systems, Inc.
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
Pin Configuration
CK-408 clock with Buffered/Unbuffered mode supporting
VDDREF 1
56 REF
Almador, Brookdale, ODEM, and Montara-G chipsets with
X1 2
55 FS1
PIII/P4 processor. Programmable for group to group skew.
X2 3
54 FS0
Output Features:
GND 4
53 CPU_STOP#*
PCICLK_F0 5
52 CPUCLKT0
3 Differential CPU Clock Pairs @ 3.3V
PCICLK_F1 6
51 CPUCLKC0
7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
PCICLK_F2 7
50 VDDCPU
3 PCI_F (3.3V) @ 33.3MHz
VDDPCI 8
49 CPUCLKT1
GND 9
48 CPUCLKC1
1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
PCICLK0 10
47 GND
1 REF (3.3V) @ 14.318MHz
**E_PCICLK1/PCICLK1 11
46 VDDCPU
5 3V66 (3.3V) @ 66.6MHz
PCICLK2 12
45 CPUCLKT2
**E_PCICLK3/PCICLK3 13
44 CPUCLKC2
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
VDDPCI 14
43 MULTSEL*
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz
GND 15
42 IREF
PCICLK4 16
41 GND
Features:
PCICLK5 17
40 FS2
Provides standard frequencies and additional 5%
PCICLK6 18
39 48MHz_USB/FS3
**
and 10% over-clocked frequencies
VDD3V66 19
38 48MHz_DOT
Supports spread spectrum modulation:
GND 20
37 VDD48
No spread, Center Spread (±0.35%, ±0.5%,
66MHZ_OUT0/3V66_2 21
36 GND
or ±0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%)
66MHZ_OUT1/3V66_3 22
35 3V66_1/VCH_CLK/FS4
**
66MHZ_OUT2/3V66_4 23
34 PCI_STOP#*
Offers adjustable PCI early clock via latch inputs
66MHZ_IN/3V66_5 24
33 3V66_0/FS5
**
Selectable 1X or 2X strength for REF via I
2
C interface
*PD# 25
32 VDD3V66
VDDA 26
31 GND
Efficient power management scheme through PD#,
GND 27
30 SCLK
CPU_STOP# and PCI_STOP#.
Vtt_PWRGD# 28
29 SDATA
Uses external 14.318MHz crystal
Stop clocks and functional control available through
56-Pin 300mil SSOP
I
2
C interface.
6.10 mm. Body, 0.50 mm. pitch TSSOP
Key Specifications:
*
These inputs have 120K internal pull-up resistors to VDD.
CPU Output Jitter <150ps
**
Internal pull-down resistors to ground.
3V66 Output Jitter <250ps
Note:
66MHz Output Jitter (Additive) (Buffered Mode) <100ps
Almador board level designs MUST use pin 22,
CPU Output Skew <100ps
66MHZ_OUT1, as the feedback connection from the
clock buffer path to the Almador (GMCH) chipset.
PLL2
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
Block Diagram
Frequency Select
Bit
FS2 FS1 FS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CPUCLK
MHz
66.66
100.00
200.00
133.33
66.66
100.00
200.00
133.33
3V66
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66MHz_OU
T (2:0)
3V66 (4:2)
MHz
66.66
66.66
66.66
66.66
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
3V66_5
MHz
66.66
66.66
66.66
66.66
Input
Input
Input
Input
PCICLK_F
PCICLK
MHz
33.33
33.33
33.33
33.33
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
3V66_5/66MHz_IN
3V66_3/66MHz_OUT1
3V66_(4,2)/66MHz_OUT(2,0)
PLL1
Spread
Spectrum
PD#
CPU_STOP#
PCI_STOP#
MULTSEL
FS (5:0)
SDATA
SCLK
V
TT
_PWRGD#
REF
CPU
DIVDER
Stop
3
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:4, 2, 0)
PCI
DIVDER
Stop
7
Control
Logic
3V66
DIVDER
E_PCICLK(1,3)/PCICLK(1,3)
2
3
PCICLK_F
(2:0)
3V66_0
Config.
Reg.
3V66_1/VCH_CLK
I REF
0542G—08/21/03
ICS950812

ICS950812 Related Products

ICS950812 ICS950812YFLFT ICS950812YGLFT
Description Frequency Generator with 200MHz Differential CPU Clocks Frequency Generator with 200MHz Differential CPU Clocks Frequency Generator with 200MHz Differential CPU Clocks
New PWM modulation method for brushless DC motors
New PWM modulation method for brushless DC motors...
安_然 DSP and ARM Processors
LM4F232 PWM Control
When sending PWM pulses, can I count the number of pulses sent by setting an interrupt for each pulse sent? Request setting method...
skytianlin Microcontroller MCU
Switching power supply help
Switching power supply help...
hhy Power technology
Well-known companies are urgently hiring hardware product quality engineers
Dear friends, the desktop department of a famous Beijing company is recruiting hardware product quality engineers. This is JD. I don’t know if it is suitable for you. If you want to consult, you can a...
aug_com Embedded System
Tutorial on connecting Putty to TPYBorad v102 development board
[p=30, null, left][color=#333333][backcolor=transparent][font=微软雅黑][size=18px]Step 1: Download Putty software[/size][/font][/backcolor][/color][/p][p=30, null, left][color=#333333][backcolor=transpare...
loktar MicroPython Open Source section
Setting up the PCB design environment
After double-clicking the design file pcb1.pcb to enter the PCB design system, you first need to set up the PCB design environment. Right-click the mouse and select Options to set up the design enviro...
ESD技术咨询 PCB Design

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2195  1024  1655  2344  2059  45  21  34  48  42 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号