Supports undriven differential CPU, SRC pair in PD#
for power management.
Pin Configuration
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.67
33.67
33.67
33.67
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
36.00
36.00
36.00
36.00
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK_F0
FS
L
A/PCICLK_F1
FS
L
B/PCICLK_F2
VDD48
**SEL24_48#/24_48MHz
USB_48MHz
GND
DOTT_ 96MHz
DOTC_96MHz
Vtt_PwrGd#/PD
PCIEXT0
PCIEXC0
VDDPCIEX
GND
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
GND
SRCCLKT
SRCCLKC
VDDSRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDPCI
PCICLK2
PCICLK1
PCICLK0
Reset#
REF0/FS
L
C
REF1
GND
X1
X2
VDDREF
SCLK
SDATA
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
IREF
GNDA
VDDA
VDDPCIEX
PCIEXT4
PCIEXC4
PCIEXT3
PCIEXC3
GND
56-Pin SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS954119
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
Pin Description
PIN # PIN NAME
1
2
3
4
5
6
7
8
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK_F0
FSLA/PCICLK_F1
PIN
TYPE
PWR
OUT
OUT
OUT
PWR
PWR
OUT
I/O
DESCRIPTION
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# .
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock
output.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values./ 3.3V PCI free running clock
output.
Power pin for the 48MHz output.3.3V
Latched select input for 24/48MHz output / 24/48MHz clock output.
1=24MHz, 0 = 48MHz.
48.00MHz USB clock
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the crystal oscillator are stopped.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
Ground pin.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Ground pin.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Supply for SRC clocks, 3.3V nominal
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FSLB/PCICLK_F2
VDD48
**SEL24_48#/24_48MHz
USB_48MHz
GND
DOTT_ 96MHz
DOTC_96MHz
Vtt_PwrGd#/PD
PCIEXT0
PCIEXC0
VDDPCIEX
GND
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
GND
SRCCLKT
SRCCLKC
VDDSRC
I/O
PWR
I/O
OUT
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
0875—05/24/04
2
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
Pin Description
PIN # PIN NAME
29
30
31
32
33
34
35
GND
PCIEXC3
PCIEXT3
PCIEXC4
PCIEXT4
VDDPCIEX
VDDA
TYPE
PWR
OUT
OUT
OUT
OUT
PWR
PWR
DESCRIPTION
Ground pin.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
3.3V power for the PLL core.
36
GNDA
PWR
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Ground pin.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values.
Real time system reset signal for frequency gear ratio change or watchdog
timer timeout. This signal is active low.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
IREF
GND
CPUCLKC1
CPUCLKT1
VDDCPU
CPUCLKC0
CPUCLKT0
SDATA
SCLK
VDDREF
X2
X1
GND
REF1
REF0/FSLC
OUT
PWR
OUT
OUT
PWR
OUT
OUT
I/O
IN
PWR
OUT
IN
PWR
OUT
I/O
52
53
54
55
56
Reset#
PCICLK0
PCICLK1
PCICLK2
VDDPCI
OUT
OUT
OUT
OUT
PWR
0875—05/24/04
3
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
General Description
ICS954119
follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets.
ICS954119
is driven with a 14.318MHz crystal.
Block Diagram
24/48MHz
48MHz, USB
PLL2
Frequency
Dividers
DOTT_96MHz
DOTC_96MHz
X1
X2
XTAL
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
Programmable
Spread
PLL1
Control
Logic
Programmable
Frequency
Dividers
STOP
Logic
SRCCLKT
SRCCLKC
PCICLK (5:0)
PCICLKF (2:0)
PCI-Express (4:0)
Reset#
I REF
SCLK
SDATA
Vtt_PWRGD#/PD
FSLA
FSLB
FSLC
Sel24/48
Power Busing
VDD
6,56
10
19,34
28
35
41
46
GND
1,5
13
20,29
25
36
38
49
Description
PCI pads and Prepad
USB _48M Hz, DOT_96M Hz, Fix P LL
Differnetial PCIEX pair
Differnetial SRC pair
Analog Core, CPU PLL
Differnetial CPU pair
Xtal, Ref, CPU PLL Digital
0875—05/24/04
4
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
General I
2
C serial interface information for the ICS954119
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
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