ICX229AL
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for CCIR B/W Video Cameras
Description
The ICX229AL is an interline CCD solid-state
image sensor suitable for CCIR B/W video cameras.
Compared with the current product ICX209AL, smear
charactristics are improved drastically and power
consumption is reduced. High sensitivity and high
saturation signal are achieved by Super HAD CCD
technology.
This chip features a field period readout system and
an electronic shutter with variable charge-storage time.
The package is a 10mm-square 14-pin DIP (Plastic).
Features
•
Low smear (–100dB Typ. at F5.6)
•
Low power consumption
(–38% compared with ICX209AL)
•
High sensitivity
(+3dB at F1.2 compared with ICX209AL)
•
High saturation signal
•
Supply voltage
12V
•
Horizontal register:
3.3V drive
•
Reset gate:
3.3V drive
•
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
•
High resolution,low dark current
•
Excellent antiblooming characteristics
•
Continuous variable-speed shutter
•
Recommended range of exit pupil distance: –20 to –100mm
Device Structure
•
Interline CCD image sensor
•
Image size:
•
Number of effective pixels:
•
Total number of pixels:
•
Chip size:
•
Unit cell size:
•
Optical black:
•
Number of dummy bits:
•
Substrate material:
14 pin DIP (Plastic)
Pin 1
2
V
12
3
Pin 8
H
40
Optical black position
(Top View)
Diagonal 4.5mm (Type 1/4)
752 (H)
×
582 (V) approx. 440K pixels
795 (H)
×
596 (V) approx. 470K pixels
4.34mm (H)
×
3.69mm (V)
4.85µm (H)
×
4.65µm (V)
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction:
Front 12 pixels, rear 2 pixels
Horizontal 22
Vertical 1 (even fields only)
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00330A1Z
ICX229AL
V
OUT
GND
Vφ
3
Vφ
1
7
6
5
4
Vφ
2
NC
3
2
Vertical Register
Note)
Horizontal Register
Note)
13
: Photo sensor
8
9
10
11
12
14
GND
V
DD
RG
V
L
Pin Description
Pin No.
1
2
3
4
5
6
7
Symbol
Vφ
4
Vφ
3
Vφ
2
Vφ
1
NC
GND
V
OUT
GND
Signal output
Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Pin No.
8
9
10
11
12
13
14
Symbol
V
DD
GND
φSUB
V
L
RG
Hφ
1
Hφ
2
Description
Supply voltage
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Absolute Maximum Ratings
Item
V
DD
, V
OUT
, RG –
φSUB
Against
φSUB
Vφ
1
, Vφ
3
–
φSUB
Vφ
2
, Vφ
4
, V
L
–
φSUB
Hφ
1
, Hφ
2
, GND –
φSUB
V
DD
, V
OUT
, RG – GND
Against GND
Vφ
1
, Vφ
2
, Vφ
3
, Vφ
4
– GND
Hφ
1
, Hφ
2
– GND
Against V
L
Vφ
1
, Vφ
3
– V
L
Vφ
2
, Vφ
4
, Hφ
1
, Hφ
2
, GND – V
L
Voltage difference between vertical clock input pins
Between input clock
pins
Storage temperature
Operating temperature
∗
1
+21V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
Hφ
1
– Hφ
2
Hφ
1
, Hφ
2
– Vφ
4
Ratings
–32 to +12
–40 to +15
–40 to +0.3
–32 to +0.3
–0.3 to +17
–7 to +14
–7 to +4.2
–0.3 to +21
–0.3 to +12
to +12
–5 to +5
–12 to +12
–30 to +80
–10 to +60
Unit
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗
1
Remarks
φSUB
Hφ
1
Hφ
2
Vφ
4
1
Block Diagram and Pin Configuration
(Top View)
ICX229AL
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Symbol
V
DD
V
L
φSUB
φRG
Min.
11.64
Typ.
12.0
∗
1
∗
2
∗
2
Max.
12.36
Unit
V
Remarks
∗
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
∗
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol
I
DD
Min.
Typ.
3.5
Max.
5.5
Unit
mA
Remarks
Clock Voltage Conditions
Item
Readout clock voltage
Symbol
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
Vφ
V
Vertical transfer clock
voltage
V
VH3
– V
VH
V
VH4
– V
VH
V
VHH
V
VHL
V
VLH
V
VLL
Horizontal transfer
clock voltage
Vφ
H
V
HL
Vφ
RG
Reset gate clock
voltage
V
RGLH
– V
RGLL
V
RGL
– V
RGLm
Substrate clock voltage Vφ
SUB
16.14
17.0
3.0
–0.05
3.0
3.3
0
3.3
Min.
11.64
–0.05
–0.2
–5.5
4.3
–0.25
–0.25
Typ.
12.0
0
0
–5.0
5.0
Max.
12.36
0.05
0.05
–4.5
5.55
0.1
0.1
0.3
0.3
0.3
0.3
3.6
0.05
3.6
0.4
0.5
17.86
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Waveform
diagram
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
Input through 0.1µF
capacitance
Low-level coupling
Low-level coupling
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
V
VL
= (V
VL3
+ V
VL4
)/2
Vφ
V
= V
VH
n – V
VL
n (n = 1 to 4)
V
VH
= (V
VH1
+ V
VH2
)/2
Remarks
–3–
ICX229AL
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer
clock and GND
Symbol
Cφ
V1
, Cφ
V3
Cφ
V2
, Cφ
V4
Cφ
V12
, Cφ
V34
Capacitance between vertical transfer
clocks
Cφ
V23
, Cφ
V41
Cφ
V13
Cφ
V24
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Vφ
1
Cφ
V12
Min.
Typ.
1200
680
220
150
82
75
22
36
5
180
82
15
12
51
Max.
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Ω
Remarks
Cφ
H1
, Cφ
H2
Cφ
HH
Cφ
RG
Cφ
SUB
R
1
, R
2
, R
3
, R
4
R
GND
Rφ
H
Rφ
RG
Vφ
2
R
1
R
2
Rφ
H
Hφ
1
Rφ
H
Hφ
2
Cφ
HH
Cφ
V23
Cφ
V13
Cφ
H1
Cφ
H2
Cφ
V1
Cφ
V41
Cφ
V24
Cφ
V2
Cφ
V4
R
GND
Cφ
V3
R
4
Cφ
V34
R
3
Vφ
4
Vφ
3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
Rφ
RG
RGφ
Cφ
RG
Reset gate clock equivalent circuit
–4–
ICX229AL
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
II
II
φM
φM
2
tf
0V
V
VT
10%
0%
tr
twh
(2) Vertical transfer clock waveform
Vφ
1
Vφ
3
V
VH1
V
VHH
V
VH
V
VHL
V
VHH
V
VHH
V
VHL
V
VHL
V
VH3
V
VHH
V
VH
V
VHL
V
VL1
V
VLH
V
VL3
V
VLH
V
VLL
V
VL
V
VL
V
VLL
Vφ
2
V
VHH
V
VHH
Vφ
4
V
VHH
V
VHH
V
VH
V
VHL
V
VH
V
VH2
V
VHL
V
VHL
V
VH4
V
VHL
V
VL2
V
VLH
V
VLH
V
VL
V
VLL
V
VL4
V
VLL
V
VL
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
Vφ
V
= V
VH
n – V
VL
n (n = 1 to 4)
–5–
stm32/stm8
京公网安备 11010802033920号
EEWORLD
