128Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
CMOS SRAM
Revision History
Rev . No.
Rev. 0.0
Rev. 1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
1. Delete Preliminary.
2. Delete 17ns, L-version and Industrial Temperature Part.
3. Delete Voh1=3.95V.
4. Delete Data Retention Characteristics and Wave form.
5. Relex operating current
Speed
Previous
Now
15ns
130mA
125mA
17ns
120mA
-
20ns
110mA
123mA
Draft Data
Feb. 1st, 1997
Jun. 1st, 1997
Remark
Design Target
Preliminary
Rev. 2.0
Feb. 6th. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 2.0
February 1998
-1-
PRELIMINARY
KM681001B
128K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating KM681001B - 15 : 125mA(Max.)
KM681001B - 20 : 123mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Standard Pin Configuration
KM681001BJ : 32-SOJ-400
KM681001BSJ : 32-SOJ-300
CMOS SRAM
GENERAL DESCRIPTION
The KM681001B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681001B uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using Samsung′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681001B is packaged
in a 400/300 mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
N.C
A
0
A
1
1
2
3
4
5
6
7
8
9
10
11
12
32 Vcc
31 A
16
30 CS
2
29 WE
28 A
15
27 A
14
26 A
13
FUNCTIONAL BLOCK DIAGRAM
A
2
A
3
A
4
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Pre-Charge Circuit
A
5
A
6
A
7
A
8
SOJ
25 A
12
24
OE
23 A
11
22 CS
1
21 I/O
8
20 I/O
7
19 I/O
6
18 I/O
5
17 I/O
4
Row Select
Memory Array
512 Rows
256x8 Columns
A
9
A
10
I/O
1
13
I/O
2
14
I/O
3
15
Vss
16
I/O
1
~ I/O
8
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
CS
1
WE
OE
PIN FUNCTION
Pin Name
A
0
- A
16
WE
CS
1
, CS
2
OE
I/O
1
~ I/O
8
V
CC
V
SS
N.C
Pin Function
Address Inputs
Write Enable
Chip Selects
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
-2-
Rev 2.0
February 1998
PRELIMINARY
KM681001B
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
Unit
V
V
CMOS SRAM
W
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5*
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+0.5**
0.8
Unit
V
V
V
V
NOTE:
*
V
IL
(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA
**
V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width≤10ns) for I≤20mA
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL,
V
OUT
= V
SS
to V
CC
Min. Cycle, 100% Duty CS
1
=V
IL,
CS
2
=V
IH,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS
1
=V
IH
or CS
2
=V
IL
f=0MHz, CS
1
≥V
CC
-0.2V or CS
2
≤0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
15ns
20ns
Min
-2
-2
-
-
-
-
-
2.4
Max
2
2
125
123
20
5
0.4
-
V
V
mA
Unit
µA
µA
mA
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
* NOTE : Capacitance is sampled and not 100% tested.
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