MC10125
Quad MECL to TTL
Translator
The MC10125 is a quad translator for interfacing data and control
signals between the MECL section and saturated logic sections of
digital systems. The MC10125 incorporates differential inputs and
Schottky TTL “totem pole” outputs. Differential inputs allow for use
as an inverting/ non–inverting translator or as a differential line
receiver. The V
BB
reference voltage is available on pin 1 for use in
single–ended input biasing. The outputs of the MC10125 go to a low
logic level whenever the inputs are left floating.
Power supply requirements are ground, +5.0 Volts and –5.2 Volts.
Propagation delay of the MC10125 is typically 4.5 ns. The MC10125
has fanout of 10 TTL loads. The dc levels are MECL 10,000 in and
Schottky TTL, or TTL out. This device has an input common mode
noise rejection of
±
1.0 Volt.
An advantage of this device is that MECL level information can be
received, via balanced twisted pair lines, in the TTL equipment. This
isolates the MECL logic from the noisy TTL environment. This device
is useful in computers, instrumentation, peripheral controllers, test
equipment and digital communications systems.
•
P
D
= 380 mW typ/pkg (No Load)
•
t
pd
= 4.5 ns typ (50% to + 1.5 Vdc out)
•
t
r
, t
f
= 2.5 ns typ (1.0 V to 2.0 V)
LOGIC DIAGRAM
2
3
6
7
10
11
14
15
V
BB
*
4
5
12
13
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
1
1
PLCC–20
FN SUFFIX
CASE 775
10125
AWLYYWW
MC10125P
AWLYYWW
MC10125L
AWLYYWW
Gnd
=
V
CC
(+5.0Vdc) =
V
EE
(-5.2Vdc) =
PIN 16
PIN 9
PIN 8
ORDERING INFORMATION
Device
MC10125L
MC10125P
MC10125FN
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
* V
BB
to be used to supply bias to the MC10125 only and bypassed (when used)
with 0.01
µF
to 0.1
µF
capacitor to ground (0 V). V
BB
can source < 1.0 mA.
When the input pin with the bubble goes positive, the output goes negative.
DIP PIN ASSIGNMENT
V
BB
A
IN
A
IN
A
OUT
B
OUT
B
IN
B
IN
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
D
IN
D
IN
D
OUT
C
OUT
C
IN
C
IN
V
CC
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10125/D
MC10125
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
–30°C
+25°C
+85°C
Pin
Under
Test
8
9
9
2
2
4
4
4
4
4
4
4
1
4
4
4
4
3
2
2
3
3,7,11,15
3,7,11,15
9
9
9
9
8
8
8
8
16
16
16
16
–2.0mA
–2.0mA
20mA
20mA
V
IHH
–1.890
–1.810
–1.700
V
ILH
–2.890
–2.850
–2.825
V
BB
From
Pin
1
V
CC
+5.0
+5.0
+5.0
V
EE
–5.2
–5.2
–5.2
Output
O tp t
Condition
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHH
V
ILH
V
BB
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
V
CC
9
9
9
9
9
9
9
9
9
9
9
9
V
EE
8
8
8
8
2,6,8,10,14
8
8
8
8
2,3,6,7,8,
10,11,14,15
8
8
Gnd
16
16
16
Characteristic
Negative Power Supply
Drain Current
Positive Power Su y
os e o e Supply
Drain Current
Input Current
Input Leakage Current
High Output Voltage
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
Indeterminate Input
Protection Tests
Symbol
I
E
I
CCH
I
CCL
I
inH
1
I
CBO
V
OH
V
OL
V
OHA
V
OLA
V
OLS1
V
OLS2
16
16
16
16
16
16
16
16
4, 16
–2.0mA
20mA
–2.0mA
20mA
20mA
20mA
Short Circuit Current
Reference Voltage
Common Mode Rejection Tests
I
OS
V
BB
V
OH
V
OL
Switching Times
(50Ω Load)
t
6+5–
t
6–5+
t
2+4–
t
2–4+
t
4+
t
4–
5
5
4
4
4
4
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
3,7,11,15
9
9
9
9
9
9
8
8
8
8
8
8
16
16
16
16
16
16
Propagation Delay
(50% to +1.5Vdc)
Rise Time
Fall Time
(+1.0V to 2.0V)
(+1.0V to 2.0V)
1. Individually test each output, apply V
IHmax
to pin under test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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4
MC10125
SWITCHING TIME TEST CIRCUIT
V
in
V
CC
+5.0 Vdc
0.1
µF
V
out
Coax
Coax
Input
Pulse Generator
Input Pulse
t+ = t- = 2.0
±0.2
ns
(20 to 80%)
-1.69 Vdc
2
3
6
7
10
11
14
15
1
0.1
µF
16
8
450
4
5
12
13
C
L
= 25 pF, including test fixture
C
L
50 ohm termination to ground located
in each scope channel input.
All input and output cables to the
scope are equal lengths of 50 ohm
coaxial cable. Wire length should be
< 1/4 inch from TP
in
to input pin and
TP
out
to output pin.
V
BB
One input from each gate must be tied to V
BB
(Pin 1) during testing.
0.1
µF
-5.2 Vdc
V
EE
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5
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