INCH-POUND
MIL-M-38510/50F
20 October 2004
SUPERSEDING
MIL-M-38510/50E
30 April 1984
MILITARY SPECIFICATION
MICROCIRCUITS, DIGITAL, CMOS, NAND GATES,
MONOLITHIC SILICON, POSITIVE LOGIC
Reactivated after 20 October 2004 and may be used for new and existing designs and acquisitions.
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF 38535
1. SCOPE
1.1 Scope. This specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits.
Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance (RHA)
are provided and are reflected in the complete Part or Identifying Number (PIN). For this product, the requirements of
MIL-M-38510 have been superseded by MIL-PRF-38535 (see 6.3).
1.2 Part or identifying number (PIN). The PIN is in accordance with MIL-PRF-38535 and as specified herein.
1.2.1 Device types. The device types are as follows:
Device type
01
02
03
51
52
53
Circuit
Quadruple 2-input NAND gate
Dual 4-input NAND gate
Triple 3-input NAND gate
Quadruple 2-input NAND gate
Dual 4-input NAND gate
Triple 3-input NAND gate
1.2.2 Device class. The device class is the product assurance level as defined in MIL-PRF-38535.
1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows:
Outline letter
A
C
D
T
X 1/ 2/
Y 1/ 2/
Descriptive designator
GDFP5-F14 or CDFP6-F14
GDIP1-T14 or CDIP2-T14
GDFP1-F14 or CDFP2-F14
CDFP3-F14
GDFP5-F14 or CDFP6-F14
GDFP1-F14 or CDFP2-F14
Terminals
14
14
14
14
14
14
Package style
Flat pack
Dual-in-line
Flat pack
Flat pack
Flat pack, except A dimension
equals 0.1” (2.54 mm) max
Flat pack, except A dimension
equals 0.1” (2.54 mm) max
1/ As an exception to MIL-PRF-38535, appendix A, for case outlines X and Y only, the leads of bottom brazed
ceramic packages (i.e., configuration 2 of case outlines A or D) may have electroless nickel undercoating
which is 50 to 200 microinches (1.27 to 5.08
µm)
thick provided the lead finish is hot solder dip (i.e., finish
letter A) and provided that, after any lead forming, an additional hot solder dip coating is applied which extends
from the outer tip of the lead to no more than 0.015 inch (0.38 mm) from the package edge.
2/ For bottom or side brazed packages, case outlines X and Y only, the S
1
dimension may go to .000 inch
(.00 mm) minimum.
Comments, suggestions, or questions on this document should be addressed to: Commander, Defense
Supply Center Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43218-3990, or email
CMOS@dscc.dla.mil. Since contact information can change, you may want to verify the currency of this
address information using the ASSIST Online database at
http://www.dodssp.daps.mil.
AMSC N/A
FSC 5962
MIL-M-38510/50F
1.3 Absolute maximum ratings.
Supply voltage range (V
DD
- V
SS
):
Device types 01, 02, 03 ...................................................................
Device types 51, 52, 53 ...................................................................
Input current (each input) ..................................................................
Input voltage range............................................................................
Storage temperature range (T
STG
) ....................................................
Maximum power dissipation (P
D
) ......................................................
Lead temperature (soldering, 10 seconds) .......................................
Thermal resistance, junction to case (θ
JC
) .........................................
Junction temperature (T
J
) .................................................................
1.4 Recommended operating conditions.
Device types 01, 02, 03:
Supply voltage range (V
DD
- V
SS
) .................................................... 4.5 V dc to 12.5 V dc
Input low voltage range (V
IL
) ........................................................... 0.0 V to 0.85 V dc @ V
DD
= 5.0 V dc
0.0 V to 2.0 V dc @ V
DD
= 10.0 V dc
0.0 V to 2.1 V dc @ V
DD
= 12.5 V dc
Input high voltage range (V
IH
).......................................................... 3.95 V to 5.0 V dc @ V
DD
= 5.0 V dc
8.0 V to 10.0 V dc @ V
DD
= 10.0 V dc
10 V to 12.5 V dc @ V
DD
= 12.5 V dc
Device types 51, 52, 53:
Supply voltage range (V
DD
- V
SS
) .................................................... 4.5 V dc to 15.0 V dc
Input low voltage range (V
IL
) ........................................................... V
OL
= 10% V
DD
, V
OH
= 90% V
DD
0.0 V to 1.5 V dc @ V
DD
= 5.0 V dc
0.0 V to 2.0 V dc @ V
DD
= 10.0 V dc
0.0 V to 4.0 V dc @ V
DD
= 15.0 V dc
Input high voltage range (V
IH
) ......................................................... V
OL
= 10% V
DD
, V
OH
= 90% V
DD
3.5 V to 5.0 V dc @ V
DD
= 5.0 V dc
8.0 V to 10.0 V dc @ V
DD
= 10.0 V dc
11 V to 15.0 V dc @ V
DD
= 15.0 V dc
Ambient operating temperature range (T
A
) ....................................... -55°C to +125°C
Load capacitance .............................................................................. 50 pF maximum
2. APPLICABLE DOCUMENTS
2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This
section does not include documents cited in other sections of this specification or recommended for additional
information or as examples. While every effort has been made to ensure the completeness of this list, document
users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this
specification, whether or not they are listed.
2.2 Government documents.
2.2.1 Specifications and Standards. The following specifications and standards form a part of this specification to
the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 -
Integrated Circuits (Microcircuits) Manufacturing, General Specification for.
-0.5 V dc to +15.5 V dc
-0.5 V dc to +18.0 V dc
±10
mA
(V
SS
- 0.5 V)
≤
V
I
≤
(V
DD
+ 0.5 V)
-65° to +175°C
200 mW
+300°C
See MIL-STD-1835
175°C
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
MIL-STD-1835
-
-
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil
or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2
MIL-M-38510/50F
2.3 Order of precedence. In the event of a conflict between the text of this document and the references cited
herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws
and regulations unless a specific exemption has been obtained.
3. REQUIREMENTS
3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a
manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before
contract award (see 4.3 and 6.4).
3.2 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535 and as
specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the
QM plan shall not affect the form, fit, or function as described herein.
3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be
as specified in MIL-PRF-38535 and herein. Although eutectic die bonding is preferred, epoxy die bonding may be
performed. However, the resin used shall be Dupont 5504 Conductive Silver Paste, or equivalent, which is cured at
200°C
±10°C
for a minimum of 2 hours. The use of equivalent epoxies or cure cycles shall be approved by the
qualifying activity. Equivalency shall be demonstrated in data submitted to the qualifying activity for verification.
3.3.1 Logic diagrams and terminal connections. The logic diagrams and terminal connections shall be as
specified on figure 1.
3.3.2 Truth tables and logic equations. The truth tables and logic equations shall be as specified on figure 2.
3.3.3 Switching time test circuit and waveforms. The switching time test circuit and waveforms shall be as
specified on figure 3.
3.3.4 Schematic circuits. The schematic circuits shall be maintained by the manufacturer and made available to
the qualifying activity or preparing activity upon request.
3.3.5 Case outlines. The case outlines shall be as specified in 1.2.3.
3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF-38535 (see 6.6).
3.5 Electrical performance characteristics. Unless otherwise specified, the electrical performance characteristics
are as specified in table I, and apply over the full recommended ambient operating temperature range.
3.6 Electrical test requirements. The electrical test requirements for each device class shall be the subgroups
specified in table II. The electrical tests for each subgroup are described in table III.
3.7 Marking. Marking shall be in accordance with MIL-PRF-38535.
3.7.1 Radiation hardness assurance identifier. The radiation hardness assurance identifier shall be in
accordance with MIL-PRF-38535 and 4.5.4 herein.
3.8 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group
number 36 (see MIL-PRF-38535, appendix A).
3
MIL-M-38510/50F
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions 1/
V
SS
= 0 V
-55°C
≤
T
A
≤
+125°C
Unless otherwise specified
T
A
= +25°C, V
DD
= GND
V
SS
= Open, Output = Open
I
IN
= 1 mA
T
A
= +25°C, V
DD
= Open
V
SS
= GND, Output = Open
I
IN
= -1 mA
All input
V
DD
= 15 V dc
combinations
V
DD
= 18 V dc
High level output voltage
V
OH1
V
OH2
V
OH3
V
OH4
Low level output voltage
V
OL1
V
DD
= 5 V dc, I
OH
= -175
µA
Any one input = V
IL
(see table III)
V
DD
= 5 V dc, I
OH
= 0.0 A
Any one input = V
IL
(see table III)
V
DD
= 12.5 V dc, I
OH
= 0.0 A
Any one input = V
IL
(see table III)
V
DD
= 15 V dc, I
OH
= 0.0 A
V
DD
= 5 V dc, I
OL
= 175
µA
All inputs = V
IH
(see table III)
V
DD
= 5 V dc, I
OL
= 85
µA
All inputs = V
IH
(see table III)
V
OL2
V
OL3
V
OL4
Input high voltage
V
IH1
V
IH2
V
IH3
Input low voltage
V
IL1
V
IL2
V
IL3
V
DD
= 5 V dc, I
OL
= 0.0 A
All inputs = V
IH
(see table III)
V
DD
= 12.5 V dc, I
OL
= 0.0 A
All inputs = V
IH
(see table III)
V
DD
= 15 V dc, I
OL
= 0.0 A
V
DD
= 5 V dc
V
O
= 0.5 V
⏐I
O
⏐ ≤
1µA
V
DD
= 10 V dc
V
O
= 1.0 V
⏐I
O
⏐ ≤
1µA
V
DD
= 15 V dc
V
O
= 1.5 V
⏐I
O
⏐ ≤
1µA
V
DD
= 5 V dc
V
O
= 4.5 V dc
⏐I
O
⏐ ≤
1µA
V
DD
= 10 V dc
V
O
= 9.0 V dc
⏐I
O
⏐ ≤
1µA
V
DD
= 15 V dc
V
O
= 13.5 V dc
⏐I
O
⏐ ≤
1µA
Device
type
All
All
01, 02,
03
51, 52,
53
All
All
All
51, 52,
53
01
02, 03
All
All
51, 52,
53
51, 52,
53
51, 52,
53
51, 52,
53
51, 52,
53
51, 52,
53
51, 52,
53
4.2
4.95
11.25
14.95
0.5
0.7
0.05
1.25
0.05
3.5
7.0
11.0
1.5
3.0
4.0
V dc
V dc
V dc
V dc
V dc
V dc
V dc
V dc
Limits
Min
Max
1.5
-6.0
-750
Unit
Positive clamping input to
V
DD
Negative clamping input to
V
SS
Quiescent supply current
V
IC (POS)
V
IC (NEG)
I
SS
V dc
V dc
nA
See footnotes at end of the table.
4
MIL-M-38510/50F
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
V
SS
= 0 V
-55°C
≤
T
A
≤
+125°C
Unless otherwise specified
V
DD
= 5 V dc
V
IN
= 5.0 V
V
OL
= 0.4 V dc
V
DD
= 15 V dc
V
IN
= 15 V
V
OL
= 1.5 V dc
V
DD
= 5 V dc
Any one input = V
SS
All other inputs = V
DD
V
OH
= 4.6 V dc
V
DD
= 15 V dc
Any one input = V
SS
All other inputs = V
DD
V
OH
= 13.5 V dc
Measure inputs
sequentially
V
DD
= 15 V dc
V
DD
= 18 V dc
Measure inputs
sequentially
V
DD
= 15 V dc
V
DD
= 18 V dc
V
DD
= 0 V dc, f = 1 MHz,
T
A
= 25°C
V
DD
= 5 V dc, C
L
= 50 pF
R
L
= 200 kΩ
(See figure 3)
Device
type
51, 52,
53
51, 52,
53
51, 52,
53
Limits
Min
Max
0.36
Unit
Output low (sink)
current
I
OL1
mA dc
I
OL2
2.4
mA dc
Output high (source)
current
I
OH1
-0.36
mA dc
I
OH2
51, 52,
53
-2.4
mA dc
Input leakage current,
high
I
IH
2/
I
IL
2/
C
i
t
PHL
01, 02,
03
51, 52,
53
01, 02,
03
51, 52,
53
All
01
02
03
51
52
53
13
13
13
13
13
13
13
13
13
13
10
10
10
10
10
10
100.0
nA
Input leakage current, low
-100.0
nA
Input capacitance
Propagation delay time,
high to low level
12
300
490
265
300
490
265
225
375
225
375
450
825
375
450
825
375
pF
ns
Propagation delay time,
low to high level
t
PLH
01, 03
02
51, 53
52
ns
Transition time,
high to low level
t
THL
V
DD
= 5 V dc, C
L
= 50 pF
R
L
= 200 kΩ
(See figure 3)
01
02
03
51
52
53
ns
See footnotes at end of the table.
5
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