19-3144; Rev 1; 3/04
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
General Description
The MAX1127 quad, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction. This ADC is
optimized for low-power, high-dynamic performance for
medical imaging, communications, and instrumentation
applications. The MAX1127 operates from a 1.7V to
1.9V single supply and consumes only 563mW while
delivering a 69.6dB signal-to-noise ratio (SNR) at a
19.3MHz input frequency. In addition to low operating
power, the MAX1127 features a 675µA power-down
mode for idle periods.
An internal 1.24V precision bandgap reference sets the
ADC’s full-scale range. A flexible reference structure
allows the use of an external reference for applications
requiring increased accuracy or a different input volt-
age range.
A single-ended clock controls the conversion process.
An internal duty-cycle equalizer allows for wide varia-
tions in input-clock duty cycle. An on-chip phase-
locked loop (PLL) generates the high-speed serial
low-voltage differential signaling (LVDS) clock.
The MAX1127 provides serial LVDS outputs for data,
clock, and frame alignment signals. The output data is
presented in two’s complement or binary format.
Refer to the MAX1126 data sheet for a pin-compatible
40Msps version of the MAX1127.
The MAX1127 is available in a small, 10mm x 10mm x
0.9mm, 68-pin QFN package with exposed paddle and
is specified for the extended industrial (-40°C to +85°C)
temperature range.
Features
♦
Four ADC Channels with Serial LVDS/SLVS
Outputs
♦
Excellent Dynamic Performance
69.6dB SNR at f
IN
= 19.3MHz
92dBc SFDR at f
IN
= 19.3MHz
-87dB Channel Isolation
♦
Ultra-Low Power
135mW per Channel (Normal Operation)
1.2mW Total (Shutdown Mode)
♦
Accepts 20% to 80% Clock Duty Cycle
♦
Self-Aligning Data-Clock to Data-Output Interface
♦
♦
♦
♦
♦
Fully Differential Analog Inputs
Wide
±1.4V
P-P
Differential Input Voltage Range
Internal/External Reference Option
Test Mode for Digital Signal Integrity
LVDS Outputs Support Up to 30in FR-4 Backplane
Connections
♦
Small, 68-Pin QFN with Exposed Paddle
♦
Evaluation Kit Available (MAX1127EVKIT)
MAX1127
Ordering Information
PART
MAX1127EGK
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
68 QFN 10mm x
x 10mm x 0.9mm
Pin Configuration
LVDSTEST
INTREF
PDALL
REFIO
OV
DD
52
51 OUT0P
50 OUT0N
49 OV
DD
48 OUT1P
47 OUT1N
46 OV
DD
45 CLKOUTP
44 CLKOUTN
43 OV
DD
42 FRAMEP
41 FRAMEN
40 OV
DD
39 OUT2P
38 OUT2N
37 OV
DD
36 OUT3P
35 OUT3N
18
AV
DD
19
I.C.
20
AV
DD
21
CV
DD
22
GND
23
CLK
24
GND
25
AV
DD
26
AV
DD
27
AV
DD
28
DT
29
SLVS/LVDS
30
PLL0
31
PLL1
32
PLL2
33
PLL3
34
OV
DD
AV
DD
AV
DD
AV
DD
AV
DD
AV
DD
GND
GND
PD3
PD2
PD1
54
PD0
53
T/B
63
68
67
66
EP
65
64
62
61
60
59
58
57
56
55
Applications
Ultrasound and Medical Imaging
Positron Emission Tomography (PET) Imaging
Multichannel Communication Systems
Instrumentation
GND
IN0P
IN0N
GND
IN1P
IN1N
GND
AV
DD
AV
DD
1
2
3
4
5
6
7
8
9
MAX1127
AV
DD
10
GND 11
IN2P 12
IN2N 13
GND 14
IN3P 15
IN3N 16
GND 17
QFN
10mm x 10mm x 0.9mm
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
MAX1127
ABSOLUTE MAXIMUM RATINGS
AV
DD
to GND.........................................................-0.3V to +2.0V
CV
DD
to GND ........................................................-0.3V to +3.6V
OV
DD
to GND ........................................................-0.3V to +2.0V
IN_P, IN_N to GND...................................-0.3V to (AV
DD
+ 0.3V)
CLK to GND .............................................-0.3V to (CV
DD
+ 0.3V)
OUT_P, OUT_N, FRAME_,
CLKOUT_ to GND................................-0.3V to (OV
DD
+ 0.3V)
DT, SLVS/LVDS to GND ...........................-0.3V to (AV
DD
+ 0.3V)
PLL0, PLL1, PLL2, PLL3 to GND .............-0.3V to (AV
DD
+ 0.3V)
PD0, PD1, PD2, PD3, PDALL to GND......-0.3V to (AV
DD
+ 0.3V)
T/B,
LVDSTEST to GND ...........................-0.3V to (AV
DD
+ 0.3V)
REFIO,
INTREF
to GND............................-0.3V to (AV
DD
+ 0.3V)
I.C. to GND...............................................-0.3V to (AV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN 10mm x 10mm x 0.9mm
(derated 41.7mW/°C above +70°C)........................3333.3mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature Range (soldering, 10s)......................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 1.8V, GND = 0, external V
REFIO
= 1.24V,
INTREF
= AV
DD
, C
REFIO
to GND = 0.1µF,
f
CLK
= 65MHz (50% duty cycle), DT = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUTS (IN_P, IN_N)
Input Differential Range
Common-Mode Voltage Range
Differential Input Impedance
Differential Input Capacitance
CONVERSION RATE
Maximum Conversion Rate
Minimum Conversion Rate
Data Latency
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT)
f
IN
= 5.3MHz at -0.5dBFS
Signal-to-Noise Ratio (Note 2)
SNR
f
IN
= 19.3MHz at -0.5dBFS, T
A
≥
+25°C
f
IN
= 30.3MHz at -0.5dBFS
Signal-to-Noise and Distortion
(First Four Harmonics) (Note 2)
f
IN
= 5.3MHz at -0.5dBFS
SINAD
f
IN
= 19.3MHz at -0.5dBFS, T
A
≥
+25°C
f
IN
= 30.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
Effective Number of Bits (Note 2)
ENOB
f
IN
= 19.3MHz at -0.5dBFS, T
A
≥
+25°C
f
IN
= 30.3MHz at -0.5dBFS
66.5
66.6
69.7
69.6
69.4
69.6
69.5
69.3
11.4
11.4
11.3
Bits
dB
dB
f
SMAX
f
SMIN
65
16
6.5
MHz
MHz
Cycles
V
ID
V
CMO
R
IN
C
IN
Differential input
(Note 3)
Switched capacitor load
1.4
0.75
2
12.5
V
P-P
V
kΩ
pF
N
INL
DNL
(Note 2)
(Note 2)
Fixed external reference (Note 2)
Fixed external reference (Note 2)
12
±0.4
±0.25
±1
±1.5
Bits
LSB
LSB
% FS
% FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 1.8V, GND = 0, external V
REFIO
= 1.24V,
INTREF
= AV
DD
, C
REFIO
to GND = 0.1µF,
f
CLK
= 65MHz (50% duty cycle), DT = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Spurious-Free Dynamic Range
(Note 2)
SYMBOL
SFDR
CONDITIONS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS, T
A
≥
+25°C
f
IN
= 30.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
Total Harmonic Distortion (Note 2)
THD
f
IN
= 19.3MHz at -0.5dBFS, T
A
≥
+25°C
f
IN
= 30.3MHz at -0.5dBFS
Intermodulation Distortion
Third-Order Intermodulation
Aperture Jitter
Aperture Delay
Small-Signal Bandwidth
Full-Power Bandwidth
Output Noise
Overdrive Recovery Time
t
OR
IMD
IM3
t
AJ
t
AD
SSBW
LSBW
f
1
= 12.348685MHz at -6.5dBFS,
f
2
= 13.650845MHz at -6.5dBFS (Note 2)
(Note 2)
(Note 2)
(Note 2)
Input at -20dBFS (Notes 2 and 4)
Input at -0.5dBFS (Notes 2 and 4)
INP = IN_N
R
S
= 25Ω, C
S
= 50pF
77.5
MIN
TYP
93.3
92
88.9
-91
-91
-88
91.2
95.7
<0.4
1
100
100
0.35
1
dBc
dBc
ps
RMS
ns
MHz
MHz
LSB
RMS
Clock
cycles
-77.5
dBc
dBc
MAX
UNITS
MAX1127
INTERNAL REFERENCE (INTREF = GND, bypass REFIO to GND with 0.1µF)
INTREF
Internal Reference Mode
Enable Voltage
INTREF
Low-Leakage Current
REFIO Output Voltage
Reference Temperature
Coefficient
INTREF
External Reference Mode
Enable Voltage
INTREF
High-Leakage Current
REFIO Input Voltage Range
REFIO Input Current
CLOCK INPUT (CLK)
Input High Voltage
Input Low Voltage
Clock Duty Cycle
Clock Duty-Cycle Tolerance
V
CLKH
V
CLKL
50
±30
0.8 x
CV
DD
0.2 x
CV
DD
V
V
%
%
I
REFIO
V
REFIO
TC
REFIO
1.18
(Note 5)
200
1.24
100
1.30
0.1
V
µA
V
ppm/°C
EXTERNAL REFERENCE (INTREF = AV
DD
)
(Note 5)
AV
DD
-
0.1V
200
1.24
<1
V
µA
V
µA
_______________________________________________________________________________________
3
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
MAX1127
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 1.8V, GND = 0, external V
REFIO
= 1.24V,
INTREF
= AV
DD
, C
REFIO
to GND = 0.1µF,
f
CLK
= 65MHz (50% duty cycle), DT = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Input Leakage
Input Capacitance
SYMBOL
DI
IN
DC
IN
0.8 x
AV
DD
0.2 x
AV
DD
Input at GND, except PLL2 and PLL3
Input Leakage
Input Capacitance
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
POWER-DOWN
PD Fall to Output Enable
PD Rise to Output Disable
POWER REQUIREMENTS
AV
DD
Supply Voltage
OV
DD
Supply Voltage
CV
DD
Supply Voltage
AV
DD
OV
DD
CV
DD
1.7
1.7
1.7
1.8
1.8
1.8
1.9
1.9
3.6
V
V
V
t
ENABLE
t
DISABLE
132
10
µs
ns
DI
IN
DC
IN
V
OHDIFF
V
OCM
t
R
t
F
V
OHDIFF
V
OCM
t
R
t
F
R
TERM
= 100Ω
R
TERM
= 100Ω
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω
R
TERM
= 100Ω
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω, C
LOAD
= 5pF
250
1.125
150
150
240
220
120
120
Input at AV
DD
, except PLL2 and PLL3
PLL2 and PLL3 only
5
450
1.375
LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0)
mV
V
ps
ps
mV
mV
ps
ps
5
80
200
pF
µA
Input at GND
Input at AV
DD
5
CONDITIONS
MIN
TYP
MAX
5
80
UNITS
µA
pF
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL,
T/B)
Input High Threshold
Input Low Threshold
V
IH
V
IL
V
V
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
4
_______________________________________________________________________________________
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 1.8V, GND = 0, external V
REFIO
= 1.24V,
INTREF
= AV
DD
, C
REFIO
to GND = 0.1µF,
f
CLK
= 65MHz (50% duty cycle), DT = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
PDALL = 0, all channels
active
PDALL = 0, all channels
active, DT = 1
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
PDALL = 1, global power
down, PD[3:0] =1111, no
clock input
PDALL = 0, all channels
active
PDALL = 0, all channels
active, DT = 1
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
PDALL = 1, global power-
down, PD[3:0] =1111, no
clock input
CV
DD
Supply Current
Power Dissipation
TIMING CHARACTERISTICS
(Note 6)
Data Valid to CLKOUT Rise/Fall
t
OD
f
CLK
= 65MHz, Figure 5 (Notes 6 and 7)
(t
SAMPLE
/
(t
SAMPLE
/
t
SAMPLE
/
24)
24)
24
- 0.15
+ 0.15
t
SAMPLE
/
12
t
SAMPLE
/
12
(t
SAMPLE
/
(t
SAMPLE
/
t
SAMPLE
/
24)
24)
24
- 0.15
+ 0.15
(t
SAMPLE
/ (t
SAMPLE
/ (t
SAMPLE
/
2)
2)
2)
+0.9
+1.3
+1.7
ns
I
CVDD
P
DISS
CV
DD
is used only to bias ESD-protection
diodes on CLK input, Figure 2
f
IN
= 19.3MHz at -0.5dBFS
MIN
TYP
257
257
82
23
300
µA
MAX
295
mA
UNITS
MAX1127
AV
DD
Supply Current
I
AVDD
f
IN
=
19.3MHz at
-0.5dBFS
56
72
42
37
375
65
mA
OV
DD
Supply Current
I
OVDD
f
IN
=
19.3MHz at
-0.5dBFS
µA
0
563
648
mA
mW
CLKOUT Output Width High
CLKOUT Output Width Low
t
CH
t
CL
Figure 5
Figure 5
ns
ns
FRAME Rise to CLKOUT Rise
t
CF
Figure 4 (Note 7)
ns
Sample CLK Rise to Frame Rise
t
SF
Figure 4 (Notes 7 and 8)
ns
_______________________________________________________________________________________
5
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