500P52N912LN4H datasheet, PDF - EEWORLD Datasheet

500P52N912LN4H: DescriptionCeramic Capacitor, Ceramic, 50V, 15% +Tol, 15% -Tol, NP0, -/+30ppm/Cel TC, 0.0091uF,; CategoryPassive components capacitor; File Size836KB，6 Pages; ManufacturerJohanson Dielectrics

Download Datasheet Parametric View All

500P52N912LN4H Overview

Ceramic Capacitor, Ceramic, 50V, 15% +Tol, 15% -Tol, NP0, -/+30ppm/Cel TC, 0.0091uF,

Parameter Name	Attribute value
Objectid	862069803
package instruction	,
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	6
capacitance	0.0091 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	18.161 mm
JESD-609 code	e0
length	37.91 mm
negative tolerance	15%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package form	DIP
positive tolerance	15%
Rated (DC) voltage (URdc)	50 V
series	P(OTHER)
Temperature characteristic code	NP0
Temperature Coefficient	30ppm/Cel ppm/°C
Terminal surface	Tin/Lead (Sn60Pb40)
Terminal pitch	2.54 mm
width	22.098 mm

What is the difference between the op amp's speed indicators, Slew rate and Rise time?: I have NE5532, NE5534, OP07, OP27, and OP37. I need a high-speed op amp that can be used as a follower for laser ranging. I read some manuals and found that the two indicators, Slew rate and Rise time...; 魔双月壁 Analog electronics

【Design Tools】MicroBlaze Support Example Xilkernel Example: This example details a Xilinx embedded system implemented using an embedded development kit, showcasing the features of the Xilkernel on a Microblaze soft processor. The hardware design used to demons...; GONGHCU FPGA/CPLD

Here are some Verilog books for you to read (continued): There is another book by Xia Yuwen that is too big to upload. I would like to contact you. The title of the book is "Verilog Digital System Design Tutorial [Xia Yuwen].rar"...; zhangkai0215 FPGA/CPLD

Circuit Question: I don't know what the device marked 3MS is in the circuit diagram?...; Benedict Integrated technical exchanges

18B20 Program: sbit DQ =P2^1; //Define the port according to the actual situation typedef unsigned char byte;typedef unsigned int word; //延时void delay(word useconds){ for(;useconds0;useconds--);} //Reset byte ow_res...; 破茧佼龙 MCU

FPGA development board schematic + example code: Yesterday I gave you two programs written in VHDL. Today I will share the Verilog routines. In fact, many large companies are currently developing with VHDL. It has strict syntax and standardized form...; super红红55 FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components