NXP Semiconductors
Advance Information
Document Number: MC33909
Rev. 4.0, 8/2016
System basis chip with DC/DC and
multiple switch-to-ground interface
This SMARTMOS IC integrates the common functionality of system basis chips
with switch detection inputs. The device works as an advanced power
management unit for the MCU and additional integrated circuits such as
sensors, CAN transceivers, and eXtreme switches. It has one built-in enhanced
high-speed CAN interface (ISO 11898-2 and -5), with local and bus failure
diagnostics, protection and fail-safe operation mode, and includes four LINs,
compatible with specification 2.1 and SAEJ2602-2.
The IC starts operating when the VBATP (reverse battery protected) pin
reaches 5.3 V maximum. The device requires a reverse blocking ultrafast or
Schottky diode for operation. The VPRE supply operating in Buck/Boost mode
allows functional operation of the IC from 2.5 V to 35 V on VBATP. The VPRE
pin supplies the source voltage for the VDD, VAUX, CAN5V, and SG power
rails.
Switch-to-ground inputs are available for switch detection and supply
configurable pulsed wetting current, with low sustain current levels for
improved thermal and power management. The IC can be programmed to
wake-up when a change of state is detected on any input. The device also
implements an innovative and advanced fail-safe state machine and concept
solution.
Features
• VDD rail (3.3 V or 5.0 V) operates down to 2.5 V on VBATP (provided by
V
PRE
Buck/Boost)
• VAUX rail (3.3 V or 5.0 V) capable of surviving short-to-battery (40 V)
conditions
• Low Q current operation for low-power sleep mode, typ. 125
μA
• Secured SPI and advanced watchdog
• SAFE_B pin for limp home mode
• Six switch to GND inputs with selectable wake-up in change of state
• Analog multiplexer
33909
SYSTEM BASIS CHIP
AD SUFFIX (PB-FREE)
48 PIN LQFP-EP
98ASA00737D
Applications
• Front/rear body controllers
• Gateway modules
• Electric power steering
• Power train
VSW
VPREGATE
VPRE VAUXE VAUXB VAUX
VDDE
VDDB
VDD
V
BAT
V
BAT
PI Filter
BOOT
VBAT_SMPS
VBATP
VBATSNS
WDI
SG0
SG1
SG2
SG3
SG4
SG5
CANH
VDD
SAFE_B
AMUX
RST_B
INT_B
MOSI
MISO
SCLK
CS_B
RXD_L0:RXD_L3
TXD_L0:TXD_L3
RXD_C
TXD_C
CAN5V
MCU
SPI
CAN Bus
VBATP
CANL
LIN_0
LIN_1
LIN_2
LIN_3
LIN Bus
LIN Bus
LIN Bus
LIN Bus
GND LIN
GND
CANGND
Figure 1. 33909AD simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
ORDERABLE PARTS
1
Orderable parts
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided
on the web. To determine the orderable part numbers for this device, go to
http://www.freescale.com
and perform a part number search
for the following device numbers.
Table 1. Orderable part variations
Part number
MC33909N5AD
MC33909L5AD
MC33909D5AD
MC33909Q5AD
MC33909N3AD
MC33909L3AD
MC33909D3AD
MC33909Q3AD
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
3.3 V
-40 °C to 125 °C
7.0 x 7.0,
48 LQFP
exposed pad
5.0 V
Temperature
(T
A
)
Package
VDD output
voltage
CAN
interface(s)
LIN interface(s)
0
1
2
1
4
0
1
2
4
6
(1)
Switch to GND
inputs
Notes
33909
NXP Semiconductors
2
INTERNAL BLOCK DIAGRAM
2
Internal block diagram
BOOT VSW VPRE VPREGATE
VBATP_SMPS
VBATP
VBATSNS
Power Supply
POR
Sleep State
Internal rails
Bandgap
V
PRE
Regulator
V
DD
Regulator
VDDE
VDDB
VDD
VAUXE
VAUXB
VAUX
SAFE_B
RESET_B
WDI
250 mV accuracy
Digital Control
Logic
VAUX
Regulator
Fail-safe
Power Management
State Machine
Inputs
V
PRE
6-20
mA
V
PRE
2.0
mA
V
PRE
SG0
SG0
SG1
SG2
SG3
SG4
SG5
6-20
mA
V
PRE
1.0
mA
(Low-power
mode)
To SPI
CANH
Enhanced High
Speed CAN
Physical
Interface
CANL
TXD_C
RXD_C
3.5 V
REF
comparator
V
PRE
2.0
mA
V
PRE
SG5
5V CAN
Regulator
CANGND
CAN5V
1.0
mA
(Low-power
mode)
To SPI
Temperature
Monitor and
Control
Internal
2.5 V
TXD_Lx
LIN
Interface
RXD_Lx
LINx
3.5 V
REF
comparator
Internal
2.5 V
V
PRE
Internal
2.5 V
V
BATP
V
DD
40
µA
Oscillator and
Clock Control
25
SPI Interface
and Control
MUX
VDD
control
V
DD
CS_B
SCLK
MOSI
MISO
AMUX
GND LIN
Internal
2.5 V
V
DD
125 kΩ
+
-
GND1/2
Interrupt
Control
INT_B
Figure 2. 33909AD simplified internal block diagram
33909
3
NXP Semiconductors
INTERNAL BLOCK DIAGRAM
2.1
Pin connections
VBAT_SMPS
VPRGATE
VBATSNS
VBATP
BOOT
VDDB
38
Transparent Top View
48
47
46
45
44
43
42
41
40
39
37
VDDE
VSW
GND
VDD
SG1
SG0
SG2
SG3
SG4
LIN0
LIN1
GNDLIN
LIN3
LIN2
SG5
AMUX
RST_B
TXD_L0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
EP
31
30
29
28
27
26
25
VAUXE
VPRE
VAUXB
VAUX
RXD_C
TXD_C
CANH
CANL
GNDCAN
CAN5V
SAFE_B
MISO
INT_B
TXD_L1
TXD_L2
RXD_L0
RXD_L1
RXD_L2
TXD_L3
Figure 3. 33909AD pin connections
A functional description of each pin can be found in the
Functional device operation
section.
Table 2. 33909 pin definitions
Pin number
Pin name
Pin function
Definition
–
1-3, 9, 47, 48
4
5
6
7
8
11
10
12
EP
SG0 - SG5
LIN0
LIN1
GND LIN
LIN3
LIN2
RST_B
AMUX
TXD_L0
Ground
Input
Input/Output
Input/Output
Ground
Input/Output
Input/Output
Input/Output
Output
Input
Exposed pad – connect to the ground plane
Switch to Ground inputs
LIN0 bus input/output connected to the LIN bus
LIN1 bus input/output connected to the LIN bus
Ground for LIN 0 - 3 bus
LIN3 bus input/output connected to the LIN bus
LIN2 bus input/output connected to the LIN bus
This is the device reset output whose main function is to reset the MCU. This pin has an internal pull-up
to VDD. RESET_B input voltage is also monitored in order to detect external reset and safe conditions.
Analog multiplex output
LIN0 bus transmit data input. Includes an internal pull-up resistor to VDD
RXD_L3
CS_B
SCLK
MOSI
WDI
33909
NXP Semiconductors
4
INTERNAL BLOCK DIAGRAM
Table 2. 33909 pin definitions (continued)
Pin number
Pin name
Pin function
Definition
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
RXD_L0
WDI
INT_B
TXD_L1
RXD_L1
RXD_L2
TXD_L2
TXD_L3
RXD_L3
MOSI
SCLK
CS_B
MISO
SAFE_B
CAN5V
GNDCAN
CANL
CANH
TXD_C
RXD_C
VAUX
VAUXB
VPRE
VAUXE
VDDE
VDDB
VDD
VPREGATE
GND
VSW
BOOT
VBATP_SMPS
VBATP
VBATSNS
Output
Input
Output
Input
Output
Output
Input
Input
Output
Input / SPI
Input / SPI
Input / SPI
Output / SPI
Output
Output
Ground
Output
Output
Input
Output
Input
Output
Input
Input
Input
Output
Input
Output
Ground
Output
Input
Power
Power
Input
LIN0 bus receive data output
Watchdog inhibit
Open drain output to the MCU is used to indicate an input switch change of state.
LIN1 bus transmit data input. Includes an internal pull-up resistor to VDD
LIN1 bus receive data output
LIN2 bus receive data output
LIN2 bus transmit data input. Includes an internal pull-up resistor to VDD
LIN3 bus transmit data input. Includes an internal pull-up resistor to VDD
LIN3 bus receive data output
SPI control data input pin from the MCU
SPI control clock input pin
SPI control chip select bar input pin. Logic [0] allows data to be transferred in.
Provides digital data from 33909 to the MCU
Output of the safe circuitry. The pin is asserted LOW in case a safe condition is detected (e.g.: software
watchdog is not triggered, V
DD
low, issue on reset pin, etc.). Open drain structure.
Output voltage for the embedded CAN interface. A capacitor must be connected to this pin.
Power ground for the embedded CAN interface
CAN low output
CAN high output
CAN bus transmit data input. Internal pull-up to V
DD
CAN bus receive data output
Output pin for the auxiliary voltage
Base connection for the external PNP transistor
Supply for VDD, VAUX, CAN5V, and SG Inputs
Collector connection for the external PNP transistor
Emitter connection for the external LDO
Base connection for the external LDO
V
DD
supply voltage
Gate control for low-side FET
Ground for logic and analog (GND1 and GND2)
Switching output
Boot capacitor to VSW
Supply for SMPS power rail. This pin requires external reverse battery protection.
Battery supply input pin. This pin requires external reverse battery protection. Supplies internal voltage
except SMPS.
Battery sense input. A 1.0 k
Ω
external resistor required to pass battery transients.
33909
5
NXP Semiconductors
Analogue and Mixed Signal
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