Data Sheet
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.45 GHz to 1.80 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
2 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
2 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in a 48-lead LFCSP
12-Output Clock Generator with
Integrated 1.6 GHz VCO
AD9517-4
FUNCTIONAL BLOCK DIAGRAM
CP
LF
SWITCHOVER
AND MONITOR
REF1
REFIN
REF2
STATUS
MONITOR
PLL
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
Δt
Δt
Δt
Δt
LVPECL
LVPECL
LVDS/CMOS
LVDS/CMOS
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Figure 1.
The
AD9517-4
features four LVPECL outputs (in two pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
For applications that require additional outputs, a crystal reference
input, zero-delay, or EEPROM for automatic configuration at
startup, the
AD9520
and
AD9522
are available. In addition,
the
AD9516
and
AD9518
are similar to the
AD9517
but have
a different combination of outputs.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The
AD9517-4
is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The
AD9517-4
is specified for operation over the industrial
range of −40°C to +85°C.
1
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The
AD9517-4
provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz
to 1.80 GHz. Optionally, an external VCO/VCXO of up to
2.4 GHz can be used.
1
The
AD9517-4
emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
AD9517 is used throughout the data sheet to refer to all the members of the
AD9517 family. However, when AD9517-4 is used, it refers to that specific
member of the AD9517 family.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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SERIAL CONTROL PORT
AND
DIGITAL LOGIC
AD9517-4
AD9517-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs ............................................................................... 6
Timing Characteristics ................................................................ 8
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used) .............................................................. 9
Clock Output Absolute Phase Noise (Internal VCO Used) .. 10
Clock Output Absolute Time Jitter (Clock Generation
Using Internal VCO) .................................................................. 11
Clock Output Absolute Time Jitter (Clock Cleanup
Using Internal VCO) .................................................................. 11
Clock Output Absolute Time Jitter (Clock Generation
Using External VCXO) .............................................................. 11
Clock Output Additive Time Jitter (VCO Divider
Not Used)..................................................................................... 12
Clock Output Additive Time Jitter (VCO Divider Used) ..... 12
Delay Block Additive Time Jitter .............................................. 13
Serial Control Port ..................................................................... 13
PD, SYNC, and RESET Pins ..................................................... 14
LD, STATUS, and REFMON Pins ............................................ 14
Power Dissipation ....................................................................... 15
Timing Diagrams ............................................................................ 16
Absolute Maximum Ratings.......................................................... 17
Thermal Resistance .................................................................... 17
Data Sheet
ESD Caution................................................................................ 17
Pin Configuration and Function Descriptions........................... 18
Typical Performance Characteristics ........................................... 20
Terminology .................................................................................... 26
Detailed Block Diagram ................................................................ 27
Theory of Operation ...................................................................... 28
Operational Configurations ...................................................... 28
Digital Lock Detect (DLD) ....................................................... 37
Clock Distribution ..................................................................... 41
Reset Modes ................................................................................ 49
Power-Down Modes .................................................................. 50
Serial Control Port ......................................................................... 51
Serial Control Port Pin Descriptions ....................................... 51
General Operation of Serial Control Port ............................... 51
The Instruction Word (16 Bits) ................................................ 52
MSB/LSB First Transfers ........................................................... 52
Thermal Performance .................................................................... 55
Control Registers ............................................................................ 56
Control Register Map Overview .............................................. 56
Control Register Map Descriptions ......................................... 59
Applications Information .............................................................. 76
Frequency Planning Using the AD9517 .................................. 76
Using the AD9517 Outputs for ADC Clock Applications .... 76
LVPECL Clock Distribution ..................................................... 77
LVDS Clock Distribution .......................................................... 77
CMOS Clock Distribution ........................................................ 78
Outline Dimensions ....................................................................... 79
Ordering Guide .......................................................................... 79
Rev. E | Page 2 of 80
Data Sheet
REVISION HISTORY
3/13—Rev. D to Rev. E
Changes to Table 52 ........................................................................ 57
Changes to Table 57 ........................................................................ 70
1/12—Rev. C to Rev. D
Changes to Table 62 ........................................................................75
5/11—Rev. B to Rev. C
Changes to Features, Applications, and General Description
Sections ............................................................................................... 1
Change to CPRSET Pin Resistor Parameter, Table 1 .................... 4
Changes to Table 2 ............................................................................ 4
Changes to Table 4 ............................................................................ 6
Changes to Logic 1 Current and Logic 0 Current
Parameters, Table 15 .......................................................................14
Changes to Table 20 ........................................................................18
Change to Caption, Figure 8 ..........................................................20
Change to Caption, Figure 15 ........................................................21
Change to Captions, Figure 25 and Figure 26 .............................23
Added Figure 41; Renumbered Sequentially ...............................25
Changes to On-Chip VCO Section ...............................................34
Changes to Reference Switchover Section ...................................35
Changes to Prescaler Section and Change to
Comments/Conditions Column, Table 28 ...................................36
Changes to Automatic/Internal Holdover Mode Section
and Frequency Status Monitors Section .......................................39
Changes to VCO Calibration Section ...........................................40
Changes to Clock Distribution Section ........................................41
Changes to Write Section ...............................................................51
Change to The Instruction Word (16 Bits) Section ....................52
Change to Figure 65 ........................................................................53
Change to Thermal Performance Section ....................................55
Changes to Register Address 0x01C, Bits[4:3], Table 52............56
Changes to Address 0x017, Bits[1:0] and Address 0x018,
Bits[2:0], Table 54 ............................................................................62
Changes to Register Address 0x01C, Bits[5:1], Table 54............64
Change to LVPECL Clock Distribution Section .........................77
5/10—Rev. A to Rev. B
Changes to Default Values of LVDS/CMOS Outputs
Section in Table 52 ..........................................................................56
Changes to Register 0x140, Bit 0; Register 0x142, Bit 0;
Register 0x143, Bit 0 in Table 57 ...................................................69
Updated Outline Dimensions, Changes to Ordering Guide .....78
1/10—Rev. 0 to Rev. A
AD9517-4
Added 48-Lead LFCSP Package (CP-48-8) .................... Universal
Changes to Features, Applications, and General Description..... 1
Change to CPRSET Pin Resistor Parameter .................................. 4
Changes to Table 4 ............................................................................ 6
Changes to V
CP
Supply Parameter................................................. 14
Changes to Table 19 ........................................................................ 16
Added Exposed Paddle Notation to Figure 6; Changes to
Table 20 ............................................................................................. 17
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 22 .......... 27
Changes to Table 24 ........................................................................ 29
Change to Configuration and Register Settings Section ........... 31
Change to Phase Frequency Detector (PFD) Section ................ 32
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections ......... 33
Change to Figure 46; Added Figure 47......................................... 33
Changes to Reference Switchover and VCXO/VCO
Feedback Divider N—P, A, B, R Sections .................................... 34
Changes to Table 28 ........................................................................ 35
Change to Holdover Section .......................................................... 37
Changes to VCO Calibration Section........................................... 39
Changes to Clock Distribution Section........................................ 40
Change to Clock Frequency Division Section;
Change to Table 34 .......................................................................... 41
Changes to Channel Dividers—LVDS/CMOS Outputs
Section; Change to Table 39 ........................................................... 43
Change to Write Section ................................................................ 50
Change to MSB/LSB First Transfers ............................................. 51
Change to Figure 64 ........................................................................ 52
Added Thermal Performance Section .......................................... 54
Changes to 0x003 Register Address .............................................. 55
Changes to Table 53 ........................................................................ 58
Changes to Table 54 ........................................................................ 59
Changes to Table 55 ........................................................................ 65
Changes to Table 56 ........................................................................ 67
Changes to Table 57 ........................................................................ 69
Changes to Table 58 ........................................................................ 71
Changes to Table 59 ........................................................................ 72
Changes to Table 60 and Table 61 ................................................. 74
Added Frequency Planning Using the AD9517 Section ............ 75
Changes to Figure 70 and Figure 72; Added Figure 71 .............. 76
Changes to LVDS Clock Distribution Section ............................ 76
Added Exposed Paddle Notation to Outline Dimensions ......... 78
Changes to Ordering Guide ........................................................... 78
7/07—Revision 0: Initial Version
Rev. E | Page 3 of 80
AD9517-4
SPECIFICATIONS
Data Sheet
Typical is given for V
S
= V
S_LVPECL
= 3.3 V ± 5%; V
S
≤ V
CP
≤ 5.25 V; T
A
= 25°C; R
SET
= 4.12 kΩ; CP
RSET
= 5.1 kΩ, unless otherwise noted.
Minimum and maximum values are given over full V
S
and T
A
(−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
V
S
V
S_LVPECL
V
CP
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
Min
3.135
2.375
V
S
2.7
Typ
3.3
Max
3.465
V
S
5.25
10
Unit
V
V
V
kΩ
kΩ
nF
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);
actual current can be calculated by CP_lsb = 3.06/CPRSET; connect
to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
4.12
5.1
220
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (K
VCO
)
Tuning Voltage (V
T
)
Frequency Pushing (Open Loop)
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
0
250
Min
1450
50
0.5
1
−109
−128
V
CP
−
0.5
Typ
Max
1800
Unit
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
Test Conditions/Comments
See
Figure 15
See
Figure 10
V
CP
≤ V
S
when using internal VCO; outside of this range,
the CP spurs may increase due to CP up/down mismatch
f = 1625 MHz
f = 1625 MHz
Differential mode (can accommodate single-ended input by ac
grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled; be careful
to match V
CM
(self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew rate
(see
Figure 14
); the input sensitivity is sufficient for ac-coupled
LVDS and LVPECL signals
Self-bias voltage of REFIN
1
Self-bias voltage of REFIN
1
Self-biased
1
Self-biased
1
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/µs
Slew rate > 50 V/µs; CMOS levels
Should not exceed V
S
p-p
250
MHz
mV p-p
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Pulse Width High/Low
Input Capacitance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
1.35
1.30
4.0
4.4
20
0
1.60
1.50
4.8
5.3
1.75
1.60
5.9
6.4
250
250
V
V
kΩ
kΩ
MHz
MHz
V p-p
V
V
µA
ns
pF
0.8
2.0
−100
1.8
2
100
45
1.3
2.9
6.0
0.8
+100
This value determines the allowable input duty cycle and is the
amount of time that a square wave is high/low
Each pin, REFIN/REFIN (REF1/REF2)
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
MHz
MHz
ns
ns
ns
Rev. E | Page 4 of 80
Data Sheet
Parameter
CHARGE PUMP (CP)
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
CP
RSET
Range
I
CP
High Impedance Mode Leakage
Sink-and-Source Current Matching
I
CP
vs. CP
V
I
CP
vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
Min
Typ
Max
Unit
AD9517-4
Test Conditions/Comments
CP
V
is CP pin voltage; V
CP
is charge pump power supply voltage
Programmable
With CP
RSET
= 5.1 kΩ
CP
V
= V
CP
/2 V
4.8
0.60
2.5
2.7/1
0
1
2
1.5
2
mA
mA
%
kΩ
nA
%
%
%
0.5 < CP
V
< V
CP
− 0.5 V
0.5 < CP
V
< V
CP
− 0.5 V
CP
V
= V
CP
/2 V
See the
VCXO/VCO Feedback Divider N—P, A, B, R
section
300
600
900
200
1000
2400
3000
3000
300
Off
330
440
550
660
770
880
990
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
A, B counter input frequency (prescaler input frequency divided by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see
Table 54
The PLL in-band phase noise floor is estimated by measuring the
in-band phase noise at the output of the VCO and subtracting
20 log(N) (where N is the value of the N divider)
−165
−162
−151
−143
−220
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL DIGITAL LOCK DETECT WINDOW
2
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
To Unlock After Lock (Hysteresis)
2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
1
2
3.5
7.5
3.5
7
15
11
ns
ns
ns
ns
ns
ns
Reference slew rate > 0.25 V/ns; FOM +10 log(f
PFD
) is an approxi-
mation of the PFD/CP in-band phase noise (in the flat region)
inside the PLL loop bandwidth; when running closed-loop, the
phase noise, as observed at the VCO output, is increased by
20 log(N)
Signal available at LD, STATUS, and REFMON pins when selected
by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. E | Page 5 of 80
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