Preliminary
FEATURES:
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For All Passive-Matrix Organic Light Emitting
Diode (OLED) Displays
Monochrome and Color
Small-Molecule and Polymer
Current-Sourcing Anode Drivers
CMOS High Voltage Process: 9-30V
Display Panel Supply Compatible
240 Output Channels, Cascadable
Token-Based Bidirectional Data Transfer:
Direct User Control of Scan Rate
Current Source Magnitude Control: 20 µA to
1mA
6-Bit Monochromatic/Color Gray-Scale
Tight current matching: ± 4% ± 2 µA
Intra-die, ± 3% Inter-die
Monochromatic/Color Voltage Pre-charge
Built-in A-to-D Converter Monitoring of
Display Panel Characteristics
3.3 to 5V logic supply
25 MHz Clock Frequency
Gold-Bumped Die @ 60 micron output pitch
TCP Package Option
Compatible with
Clare Micronix
200 Series
OLED Row Drivers
MXED102A
Patent Pending
240-Channel OLED Column Driver
OVERVIEW:
The MXED102 is Clare Micronix’s second-
generation OLED column driver, which directly
supports up to 240-monochromatic or 80-color
OLED pixels. The MXED102A’s exceptionally
tight current-matching of adjacent and cascaded
outputs, pre-charge options, and OLED
monitoring capability ensure uniform luminance
and high-quality gray-scaling in both
monochromatic and RGB mode.
FUNCTIONAL DESCRIPTION:
The MXED102A is capable of driving 240 columns (LED anodes) of an OLED display. Outputs are
divided into 3 groups of 80 in order to support color (red, green, blue) displays. Each group has an
individual setting for voltage precharge and current magnitude. Individual output luminance is
controlled by setting the exposure time (amount of time the current driver is on) for that output.
Device settings, such as precharge voltage, current magnitude, precharge time, color mode, and
others, are set by writing to a bank of control registers via a serial port. Some registers of the serial
port are also available for readback. Several devices may share the serial bus, but only the device
with its MASTER_IN pin pulled high will respond to a read request.
Figure 1 is a block diagram of the MXED102A. Each column output has three possible sources:
ground, to turn the LED off; a precharge voltage to bring the diode rapidly up to its threshold voltage;
and a current source, which is used to turn the diode on. A close up view of an output is shown in
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December 18, 2002
Preliminary
FUNCTIONAL DESCRIPTION - CONTINUED
MXED102A
Figure 1. The precharge feature brings the LED’s up to their threshold voltage quickly and accurately
so that the current source may immediately illuminate the diode instead of having to charge the
parasitic capacitance of the diodes up to the threshold voltage.
The MXED102A also provides two control signals to interface directly to a row driver, such as the
MXED202. The first is CLK_ROW, which is a clock signal indicating the start of a new row. The
second is PCB_ROW, indicating that precharge is completed.
Exposure data is a count of 0 to 63 CLKEX cycles, controlling how long an LED is to be turned on.
Exposure data may be written in either 6-bit mode or 18-bit mode. In 6-bit mode, all exposure data
is input on DC[5:0]. It takes 240 CLKSH cycles from the occurrence of the token-bit to write all 240
columns’ data. In 18-bit mode, red exposure data is written on DA[5:0] (columns 0, 3, 6...), green
data is written on DB[5:0] (columns 1, 4, 7,...) and blue data is written on DC[6:0] (columns 2, 5, 8,...).
This mode only requires 80 CLKSH cycles from the occurrence of the token-bit to write all locations.
Exposure data is written to a set of registers, allowing all columns to be written before the next active
row. When LE goes high, data is transferred from these registers to the column control circuits and
the new row begins.
FIGURE 1 - COLUMN OUTPUT
column output
VPre
+
-
MXED102
VDD
ISHRT
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MXED102A
VDD
VDD
VDD
VCC
COLUMNS 1, 2, AND 3
DIRTKN
LTKNB
CLKSH
DA[5:0]
6
6
Token
Latch
RTKNB
Preliminary
DB[5:0]
DC[5:0]
6
ROW_CLK
1
Bus
Demux
Data
Latch
6
Data
Latch
6
Data
Latch
6
ROW_PCB
Clock
Logic
3
FIGURE 2 - MXED102A BLOCK DIAGRAM
LE
Delay
Circuit
CLKEX
AD_IN
SAMPLE
8
A to D
Converter
Serial
Data
Interface
5
4
CLKSER
SDATA
Iref Gen
MASTER_IN
MASTER_OUT
Delay
Circuit
Down
Counter
5
5
8
8
8
Down
Counter
Down
Counter
Current
Red
Magnitude
Green
Register
Blue
Precharge
Generator
GND GNDA PRECHA PRECHB PRECHC ISHRT
Column 0
Red Out
Column 1
Green Out
Column 2
Blue Out
Column 237 Column 239Column 239
Red Out
Green Out Blue Out
do notcut this part off
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14080B
Preliminary
Table of Contents
MXED102A
FEATURES ..................................................................................................................................... 1
OVERVIEW ..................................................................................................................................... 1
FUNCTIONAL DESCRIPTION ..................................................................................................... 1-2
FIGURE 1 - COLUMN OUTPUT ..................................................................................................... 2
FIGURE 2 - MXED102A BLOCK DIAGRAM ................................................................................... 3
TABLE 1 - INPUT/OUTPUT PAD DESCRIPTIONS ..................................................................... 5-6
SERIAL CONFIGURATION BUS .................................................................................................... 7
FIGURE 3 - SERIAL PORT WRITE TIMING DIAGRAM ................................................................. 8
FIGURE 4 - SERIAL PORT READ TIMING DIAGRAM .................................................................. 8
REGISTER ADDRESS TABLES ................................................................................................ 9-11
FIGURE 5 - 6-BIT MODE TIMING ................................................................................................ 12
FIGURE 6 - 18-BIT MODE TIMING .............................................................................................. 13
FIGURE 7 - EPSON MODE TIMING ............................................................................................. 13
FIGURE 8 - COLUMN OUTPUT TIMING ...................................................................................... 15
ELECTRICAL SPECIFICATIONS ............................................................................................ 17-20
APPLICATION HINTS ................................................................................................................... 21
FIGURE 9 - PARASITIC DIODE IN PRECHARGE CIRCUIT........................................................ 21
RECOMMENDED POWER UP SEQUENCE ............................................................................... 21
RECOMMENDED PRE-CHARGE CONFIGURATIONS ............................................................... 22
POWER CONSUMPTION AND HEAT DISSIPATION .................................................................. 22
MECHANICAL SPECIFICATIONS ................................................................................................ 23
FIGURE 10 - TCP ASSEMBLY DRAWING ................................................................................... 24
DIE SPECIFICATIONS.................................................................................................................. 25
FIGURE 11 - DIE DIMENSIONAL DRAWING ............................................................................... 26
MXED102 PAD LOCATION TABLES ....................................................................................... 27-30
FIGURE 12 - BGA SPECIFICATIONS .......................................................................................... 31
ORDERING INFORMATION ......................................................................................................... 34
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14080B
Preliminary
INPUT/OUTPUT PAD DESCRIPTIONS
Name
VD D
VC C
GND
GNDA
ISHRT
I/O/A Description
High voltage supply.
Logic supply
Ground
Analog ground
MXED102A
Connect to ground. There can be high currents on this line. It
should be separated from the circuit ground pads (GND) to
prevent ground bounce.
Precharge A/B/C: Column precharge voltage outputs.
PRECHA/B/C should be tied to PRECHA/B/C of all other
column drivers to ensure a uniform display precharge and
should be bypassed to ground with a capacitor at least 50
times the display capacitance, up to a maximum of 5uF.
Master In: High input implies chip is master. This input is
pulled low internally.
Master Out: MASTER_IN delayed by 1 LE clock cycle,
sampled on rising edge of LE.
Token Shift Clock: Input signal used to shift tokens down the
length of the driver IC and latch data into the corresponding
columns. The direction of token shift is determined by
DIRTKN pin.
Left Token Bit: Input for shift right, output for shift left. Signal is
used to pass the tokens into and out of the driver IC. High
state represents the presence of token.
Right Token Bit: Input for shift left, output for shift right. Signal
is used to pass the tokens into and out of the driver IC. High
state represents the presence of token.
Row Clock: Signal intended to drive the row driver IC shift
data clock.
Row Precharge: Signal intended to drive the row driver IC
precharge input.
PRECHA,PRECHB,
PRECHC
O/A
MASTER_IN
MASTER_OUT
I
O
C LK S H
I
LTKNB
I/O
RTKNB
I/O
CLK_ROW
PCB_ROW
O
O
I = INPUT, O = OUTPUT, A = ANALOG
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14080B
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