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IDT71V124SA20PH

Description
128K X 8 STANDARD SRAM, 12 ns, PDSO32
Categorystorage   
File Size113KB,8 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT71V124SA20PH Overview

128K X 8 STANDARD SRAM, 12 ns, PDSO32

IDT71V124SA20PH Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals32
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage3.15 V
Rated supply voltage3.3 V
maximum access time12 ns
Processing package descriptionTSOP2-32
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE, THIN PROFILE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
memory width8
organize128K × 8
storage density1.05E6 deg
operating modeASYNCHRONOUS
Number of digits131072 words
Number of digits128K
Memory IC typeStandard memory
serial parallelparallel
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
IDT71V124SA/HSA
Features
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
– Commercial: 10/12/15/20ns
– Industrial: 10/12/15/20ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
Functional Block Diagram
A
0
A
16
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O
0
- I/O
7
8
I/O CONTROL
8
.
8
WE
OE
CS
CONTROL
LOGIC
3873 drw 01
OCTOBER 2008
1
©2007- Integrated Device Technology, Inc.
DSC-3873/09
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