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KM681000BLP-7L

Description
128K x8 bit Low Power CMOS Static RAM
Categorystorage    storage   
File Size124KB,11 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

KM681000BLP-7L Overview

128K x8 bit Low Power CMOS Static RAM

KM681000BLP-7L Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSAMSUNG
Parts packaging codeDIP
package instructionDIP, DIP32,.6
Contacts32
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PDIP-T32
JESD-609 codee0
length41.91 mm
memory density1048576 bi
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.6
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum standby current0.00001 A
Minimum standby current2 V
Maximum slew rate0.07 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width15.24 mm
KM681000B Family
128K x8 bit Low Power CMOS Static RAM
FEATURES
¡Ü
¡Ü
PRELIMINARY
CMOS SRAM
GENERAL DESCRIPTION
The KM681000B family is fabricated by SAMSUNG's advanced
CMOS process technology. The family can support various
operating temperature ranges and have various package types
for user flexibility of system design. The family also support low
data retention voltage for battery back-up operation with low
data retention current.
¡Ü
¡Ü
¡Ü
¡Ü
Process Technology : 0.6
§-
CMOS
Organization : 128Kx8
Power Supply Voltage : Single 5.0V
¡¾
10%
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : JEDEC Standard
32-DIP, 32-SOP, 32-TSOP I R/F
PRODUCT FAMILY
Power Dissipation
Product
Family
KM681000BL
KM681000BL-L
KM681000BLE
KM681000BLE-L
KM681000BLI
KM681000BLI-L
Industrial(-40~85
¡É
)
70/100ns
Extended(-25~85
¡É
)
70/100ns
Operating
Temperature
Speed
PKG Type
Standby
(I
SB1
, Max)
100
§Ë
20
§Ë
100
§Ë
50
§Ë
100
§Ë
50
§Ë
70mA
Operating
(I
CC2
)
Commercial(0~7
¡É
)
55/70ns
32-DIP,32-SOP
32-TSOP I R/F
32-SOP
32-TSOP I R/F
32-SOP
32-TSOP I R/F
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A
0~3,
A
8~11
N.C
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
V
CC
A
15
CS
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
32-DIP
32-SOP
26
25
24
23
22
21
20
19
18
17
A
11
A
9
A
8
A
13
WE
CS
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-TSOP
Type I - Forward
OE
A
10
CS
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
V
SS
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
Y-Decoder
X-Decoder
A
4~7,
A
12~16
Cell
Array
Control Logic
CS
1
,CS
2
WE
,
OE
I/O
1
~
8
A
4
A
5
A
6
A
7
A
12
A
14
A
16
NC
V
CC
A
15
CS
2
WE
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
I/O Buffer
32-TSOP
Type I-Reverse
23
24
25
26
27
28
29
30
31
32
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
CS
1
A
10
OE
Name
A
0
~A
16
WE
Function
Address Inputs
Write Enable Input
Chip Select Inputs
Output Enable Input
Data Inputs/Outputs
Power
Ground
No Connection
CS
1
,CS
2
OE
I/O
1
~I/O
18
Vcc
Vss
N.C
Revision 0.3
April 1996
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