PALCE16V8Q-15JC datasheet, PDF

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PALCE16V8Q-15JC: DescriptionEE PLD, 25 ns, PQCC20; CategoryProgrammable logic devices Programmable logic; File Size162KB，26 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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PALCE16V8Q-15JC Overview

EE PLD, 25 ns, PQCC20

PALCE16V8Q-15JC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QLCC
package instruction	QCCJ, LDCC20,.4SQ
Contacts	20
Reach Compliance Code	unknow
Other features	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 1 EXTERNAL CLOCK
Architecture	PAL-TYPE
maximum clock frequency	45.5 MHz
JESD-30 code	S-PQCC-J20
JESD-609 code	e0
length	8.9662 mm
Dedicated input times	8
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	64
Number of terminals	20
Maximum operating temperature	75 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8.9662 mm
Base Number Matches	1

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FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25

IND: H-10/15/25, Q-20/25

PALCE16V8 Family

EE CMOS 20-Pin Universal Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all 20-pin

GAL devices

Electrically erasable CMOS technology

provides reconfigurable logic and full

testability

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for the PAL16R8

series and most of the PAL10H8 series

Outputs programmable as registered or

combinatorial in any combination

Peripheral Component Interconnect (PCI)

compliant

Programmable output polarity

Programmable enable/disable control

Preloadable output registers for testability

Automatic register reset on power up

Cost-effective 20-pin plastic DIP, PLCC, and

SOIC packages

Extensive third-party software and programmer

support through FusionPLD partners

Fully tested for 100% programming and

functional yields and high reliability

5 ns version utilizes a split leadframe for

improved performance

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with

low-power, high-speed, electrically-erasable CMOS

technology. It is functionally compatible with all 20-pin

GAL devices. The macrocells provide a universal device

architecture. The PALCE16V8 will directly replace the

PAL16R8 and PAL10H8 series devices, with the excep-

tion of the PAL16C1.

The PALCE16V8 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced to

sum-of-products form, taking advantage of the very

wide input gates available in PAL devices. The equa-

tions are programmed into the device through floating-

gate cells in the AND logic array that can be erased

electrically.

The fixed OR array allows up to eight data product terms

per output for logic functions. The sum of these products

feeds the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial with an active-

high or active-low output. The output configuration is

determined by two global bits and one local bit

controlling four multiplexers in each macrocell.

AMD’s FusionPLD program allows PALCE16V8 de-

signs to be implemented using a wide variety of popular

industry-standard design tools. By working closely with

the FusionPLD partners, AMD certifies that the tools

provide accurate, quality support. By ensuring that third-

party tools are available, costs are lowered because a

designer does not have to buy a complete set of new

tools for each device. The FusionPLD program also

greatly reduces design time since a designer can use a

tool that is already installed and familiar.

2-36

Publication#

16493

Rev.

Issue Date:

February 1996

Amendment

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