The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
1
),
an active HIGH Chip Enable (CE
2
), an active LOW Output
Enable (OE), and three-state drivers. This device has an
automatic power-down feature that reduces power
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
1
) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
I/O 0
I/O 1
SENSE AMPS
I/O 2
I/O 3
I/O 4
I/O 5
POWER
DOWN
512x 256x 8
ARRAY
CE1
CE2
WE
OE
COLUMN
DECODER
I/O 6
I/O 7
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
Cypress Semiconductor Corporation
Document #: 38-05300 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised February 14, 2005
CY62128B
MoBL
Product Portfolio
Power Dissipation
V
CC
Range (V)
Product
CY62128BLL
Industrial
Industrial
Automotive
Min.
4.5
Typ.
[2]
5.0
Max.
5.5
Speed
(ns)
55
70
70
Operating, I
CC
(mA)
Typ.
[2]
7.5
6
6
Max.
20
15
25
Standby, I
SB2
(µA)
Typ.
[2]
2.5
2.5
2.5
Max.
15
15
25
Pin Configurations
Top View
SOIC
1
2
3
4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O
0 13
I/O
1 14
I/O
2 15
GN
G
ND 16
g
gnc
G
NC
A16
A14
A12
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE
2
WE
A13
A8
A9
A11
OE
A10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
16
A
12
A
14
A
7
A
4
A
5
A
6
V
CC
NC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Reverse TSOP I
Top View
(not to scale)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
3
A
11
A
2
A
9
A
1
A
8
A
13
A
0
I/O
0
WE
I/O
1
CE
2
A
15
I/O
2
GND V
CC
NC
I/O
3
A
16
I/O
4
A
14
I/O
5
A
12
I/O
6
A
7
I/O
7
A
6
CE
1
A
5
A
10
A
4
OE
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
STSOP
Top View
(not to scale)
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Pin Definitions
Input
Input/Output
Input/Control
Input/Control
Input/Control
Input/Control
Ground
Power Supply
A
0
-A
16
. Address Inputs
I/O
0
-I/O
7
. Data lines. Used as input or output lines depending on operation
WE.
Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ
is conducted.
CE
1
. Chip Enable 1, Active LOW.
CE
2
. Chip Enable 2, Active HIGH.
OE.
Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins
GND.
Ground for the device
V
CC
. Power supply for the device
Notes:
2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production
variations as measured at V
CC
= 5.0V, T
A
= 25°C, and t
AA
= 70 ns.
Document #: 38-05300 Rev. *C
Page 2 of 11
CY62128B
MoBL
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[3]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Input
Voltage
[3]
.................................–0.5V
to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Automotive
Ambient
Temperature (T
A
)
[4]
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
CY62128B-55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Load Current
Output Leakage
Current
Output Short Circuit
Current
[5]
V
CC
Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
GND
≤
V
I
≤
V
CC
Automotive
GND
≤
V
I
≤
V
CC
,
Output Disabled
–1
Automotive
–300
7.5
20
6
6
0.1
2
0.1
0.1
2.5
15
2.5
2.5
+1
Test Conditions
V
CC
= Min., I
OH
= –1.0 mA
V
CC
= Min., I
OL
= 2.1 mA
2.2
–0.3
–1
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
2.2
–0.3
–1
–10
–1
–10
Typ.
[2]
Max.
CY62128B-70
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
+10
+1
+10
–300
15
25
1
2
15
25
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
µA
µA
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
,
CE
1
≥
V
IH
or CE
2
< V
IL
,
V
IN
≥
V
IH
or
V
IN
≤
V
IL
, f = f
MAX
Industrial,
Commercial
Automotive
Industrial
Commercial
Automotive
I
SB1
I
SB2
Automatic CE
Power-down Current
—CMOS Inputs
Industrial
Max. V
CC
,
CE
1
≥
V
CC
– 0.3V, Commercial
or CE
2
≤
0.3V,
Automotive
V
IN
≥
V
CC
– 0.3V,
or V
IN
≤
0.3V, f = 0
Thermal Resistance
[6]
Parameter
Description
Test Conditions
32 SOIC 32 TSOP 32 STSOP 32 RTSOP
66.17
30.87
97.44
26.05
105.14
14.09
97.44
26.05
Unit
°C/W
°C/W
Θ
JA
Θ
JC
Thermal Resistance Test conditions follow standard test
(Junction to Ambient) methods and procedures for
Thermal Resistance measuring thermal impedance, per
EIA / JESD51.
(Junction to Case)
Note:
3. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
4. T
A
is the “Instant On” case temperature.
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05300 Rev. *C
Page 3 of 11
CY62128B
MoBL
Capacitance
[6]
Parameter
C
IN
C
OUT
\
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
9
9
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
R2
990
Ω
R1 1800Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
990
Ω
GND
Rise TIme:
1 V/ns
R1 1800Ω
V
CC
ALL INPUT PULSES
90%
10%
90%
10%
Fall TIme:
1 V/ns
THÉVENIN EQUIVALENT
639
Ω
1.77V
OUTPUT
Data Retention Characteristics
(Over the Operating Range for “LL” version only)
Parameter
V
DR
I
CCDR
t
CDR
t
R
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V, CE
1
≥
V
CC
– 0.3V,
or CE
2
≤
0.3V, V
IN
≥
V
CC
– 0.3V or, V
IN
≤
0.3V
0
70
Conditions
Min.
2.0
1.5
15
Typ.
Max.
Unit
V
µA
ns
ns
Data Retention Waveform
V
CC
CE
1
V
CC
, min.
t
CDR
DATA RETENTION MODE
V
DR
> 2 V
V
CC
, min.
t
R
or
CE2
Document #: 38-05300 Rev. *C
Page 4 of 11
CY62128B
MoBL
Switching Characteristics
[7]
Over the Operating Range
62128B-55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[8, 9]
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[9]
CE
1
HIGH to High Z, CE
2
LOW to High Z
[8, 9]
CE
1
LOW to Power-up, CE
2
HIGH to Power-up
CE
1
HIGH to Power-down, CE
2
LOW to Power-down
Write Cycle Time
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z
[9]
WE LOW to High Z
[8, 9]
55
45
45
0
0
45
25
0
5
20
0
55
70
60
60
0
0
50
30
0
5
25
5
20
0
70
0
20
5
25
5
55
20
0
25
55
55
5
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
62128B-70
Min.
Max.
Unit
WRITE CYCLE
[10]
Switching Waveforms
Read Cycle No.1
[12, 13]
t
RC
ADDRESS
t
OHA
DATA OUT
t
AA
DATA VALID
PREVIOUS DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write, and
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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