CY7C09189V-9AC datasheet, PDF - EEWORLD Datasheet

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CY7C09189V-9AC: Description3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM; File Size417KB，18 Pages; ManufacturerCypress Semiconductor

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CY7C09189V-9AC Overview

3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM

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CY7C09079V/89V/99V

CY7C09179V/89V/99V

CY7C09079V/89V/99V

CY7C09179V/89V/99V

3.3V 32K/64K/128K x 8/9

Synchronous Dual-Port Static RAM

Features

•

True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

•

6 Flow-Through/Pipelined devices

— 32K x 8/9 organizations (CY7C09079V/179V)

— 64K x 8/9 organizations (CY7C09089V/189V)

— 128K x 8/9 organizations (CY7C09099V/199V)

•

3 Modes

— Flow-Through

— Pipelined

— Burst

• Pipelined output mode on both ports allows fast

100-MHz operation

• 0.35-micron CMOS for optimum speed/power

•

High-speed clock to data access 6.5

[1]

/7.5

[1]

/9/12 ns

(max.)

•

3.3V low operating power

— Active= 115 mA (typical)

—

Standby= 10

µA

(typical)

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally

— Shorten cycle times

— Minimize bus noise

— Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Automatic power-down

• Commercial and Industrial temperature ranges

• Available in 100-pin TQFP

• Pb-Free packages available

Logic Block Diagram

R/W

0/1

FT/Pipe

I/O

–I/O

7/8L

[2]

0/1

FT/Pipe

I/O

–I/O

7/8R

[2]

8/9

I/O

Control

15/16/17

I/O

Control

15/16/17

[3]

–A

14/15/16L

CLK

ADS

CNTEN

CNTRST

Counter/

Address

Decode

True Dual-Ported

RAM Array

Counter/

Address

Decode

–A

14/15/16R

CLK

ADS

CNTEN

CNTRST

[3]

Notes:

1. See page 6 for Load Conditions.

2. I/O

–I/O

for x8 devices, I/O

–I/O

for x9 devices.

3. A

–A

for 32K, A

–A

for 64K, and A

–A

for 128K devices.

Cypress Semiconductor Corporation

Document #: 38-06043 Rev. *B

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised May 18, 2005

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