CY7C09269V/79V/89V
CY7C09369V/89V
3.3 V 16 K / 32 K / 64 K × 16 / 18
Synchronous Dual-Port Static RAM
3.3 V 16 K / 32 K / 64 K × 16 / 18 Synchronous Dual-Port Static RAM
Features
■
■
■
■
High speed clock to data access: 7.5
[1]
, 9, 12 ns (max)
3.3 V low operating power:
❐
Active = 115 mA (typical)
❐
Standby = 10
A
(typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally:
❐
Shorten cycle times
❐
Minimize bus noise
❐
Supported in flow through and pipelined modes
Dual chip enables easy depth expansion
Upper and lower byte controls for bus matching
Automatic power down
Commercial and industrial temperature ranges
Pb-free 100-pin TQFP package available
True dual-ported memory cells that allow simultaneous access
of the same memory location
Six flow through/pipelined devices:
❐
16 K × 16 / 18 organization (CY7C09269V/369V)
❐
32 K × 16 organization (CY7C09279V)
❐
64 K × 16 / 18 organization (CY7C09289V/389V)
Three modes:
❐
Flow through
❐
Pipelined
❐
Burst
Pipelined output mode on both ports allows fast 100 MHz
operation
0.35 micron CMOS for optimum speed and power
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
LB
R
OE
R
FT/Pipe
L
[2]
I/O
8/9L
–I/O
15/17L
[3]
8/9
0/1
1b 0b 1a 0a
b
a
0a 1a 0b 1b
a
b
0/1
FT/Pipe
R
8/9
I/O
8/9R
–I/O
15/17R
8/9
[2]
I/O
Control
I/O
Control
8/9
14/15/16
[3]
I/O
0L
–I/O
7/8L
A
0L
–A
13/14/15L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
[4]
14/15/16
I/O
0R
–I/O
7/8R
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
A
0R
–A
13/14/15R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[4]
True Dual-Ported
RAM Array
Notes
1. See
Figure 4 on page 8
for Load Conditions.
2. I/O
8
–I/O
15
for × 16 devices; I/O
9
–I/O
17
for × 18 devices.
3. I/O
0
–I/O
7
for × 16 devices. I/O
0
–I/O
8
for × 18 devices.
4. A
0
–A
13
for 16K; A
0
–A
14
for 32K; A
0
–A
15
for 64K devices.
Cypress Semiconductor Corporation
Document Number: 38-06056 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 1, 2012
CY7C09269V/79V/89V
CY7C09369V/89V
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 5
Pin Definitions .................................................................. 5
Functional Description ..................................................... 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
Electrical Characteristics ................................................. 7
Capacitance ...................................................................... 7
AC Test Loads and Waveforms ....................................... 8
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 10
Read/Write and Enable Operation ................................. 17
Address Counter Control Operation ............................. 17
Ordering Information ...................................................... 18
16 K × 16 3.3 V Synchronous Dual-Port SRAM ........ 18
32 K × 16 3.3 V Synchronous Dual-Port SRAM ........ 18
16 K × 18 3.3 V Synchronous Dual-Port SRAM ........ 18
64 K × 18 3.3 V Synchronous Dual-Port SRAM ........ 18
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document Number: 38-06056 Rev. *I
Page 2 of 22
CY7C09269V/79V/89V
CY7C09369V/89V
Pin Configurations
Figure 1. 100-pin TQFP (Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
A9R
A10R
A11R
A12R
A13R
A14R
[5]
A15R
[6]
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
FT/PIPER
GND
[5]
A14L
[6]
A15L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
FT/PIPEL
CY7C09289V (64 K × 16)
CY7C09279V (32 K × 16)
CY7C09269V (16 K × 16)
A8R
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
[7]
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
A0L
[7]
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
Notes
5. This pin is NC for CY7C09269V.
6. This pin is NC for CY7C09269V and CY7C09279V.
7. For CY7C09269V and CY7C09279V, pin #18 connected to V
CC
is pin compatible to an IDT 5 V × 16 pipelined device; connecting pin #18 and #58 to GND is pin
compatible to an IDT 5 V × 16 flow through device.
Document Number: 38-06056 Rev. *I
I/O10R
GND
GND
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
VCC
Page 3 of 22
CY7C09269V/79V/89V
CY7C09369V/89V
Pin Configurations
(continued)
Figure 2. 100-pin TQFP (Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
OER
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
[8]
A14L
[9]
A15L
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
VCC
FT/PIPEL
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
A7R
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
[8]
[9]
CY7C09389V (64 K × 18)
CY7C09369V (16 K × 18)
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
I/01R
Notes
8. This pin is NC for CY7C09369V.
9. This pin is NC for CY7C09369V.
Document Number: 38-06056 Rev. *I
I/O10R
GND
GND
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
VCC
Page 4 of 22
CY7C09269V/79V/89V
CY7C09369V/89V
Selection Guide
Specifications
f
MAX2
(MHz) (Pipelined)
Max. Access Time (ns) (Clock to Data, Pipelined)
Typical Operating Current I
CC
(mA)
Typical Standby Current for I
SB1
(mA) (Both Ports TTL
Level)
Typical Standby Current for I
SB3
(A) (Both Ports CMOS
Level)
CY7C09269V/79V/89V
CY7C09369V/89V
-7
[10]
83
7.5
155
25
10
CY7C09269V/79V/89V
CY7C09369V/89V
-9
67
9
135
20
10
CY7C09269V/79V/89V
CY7C09369V/89V
-12
50
12
115
20
10
Pin Definitions
Left Port
A
0L
–A
15L
ADS
L
Right Port
A
0R
–A
15R
ADS
R
Description
Address Inputs
(A
0
–A
14
for 32K, A
0
–A
13
for 16K devices).
Address Strobe Input.
Used as an address qualifier. This signal must be asserted LOW to access
the part using an externally supplied address. Asserting this signal LOW also loads the burst counter
with the address present on the address pins.
Chip Enable Input.
To select either the left or right port, both CE
0
AND CE
1
must be asserted to their
active states (CE
0
V
IL
and CE
1
V
IH
).
Clock Signal.
This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input.
Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW.
Counter Reset Input.
Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Lower Byte Select Input.
Asserting this signal LOW enables read and write operations to the lower
byte. (I/O
0
–I/O
8
for × 18, I/O
0
–I/O
7
for × 16) of the memory array. For read operations both the LB and
OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input.
Same function as LB, but to the upper byte (I/O
8/9L
–I/O
15/17L
).
Output Enable Input.
This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input.
This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow Through/Pipelined Select Input.
For flow through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
CE
0L
, CE
1L
CLK
L
CNTEN
L
CNTRST
L
I/O
0L
–I/O
17L
LB
L
CE
0R
,CE
1R
CLK
R
CNTEN
R
CNTRST
R
I/O
0R
–I/O
17R
Data Bus Input/Output
(I/O
0
–I/O
15
for × 16 devices).
LB
R
UB
L
OE
L
R/W
L
FT/PIPE
L
GND
NC
V
CC
UB
R
OE
R
R/W
R
FT/PIPE
R
Note
10. See
Figure 4 on page 8
for Load Conditions.
Document Number: 38-06056 Rev. *I
Page 5 of 22
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