2. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper operation.
Document #: 38-05256 Rev. *K
Page 3 of 14
[+] Feedback
CY7C1061AV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65
C
to +150
C
Ambient Temperature with
Power Applied .......................................... –55
C
to +125
C
Supply Voltage on V
CC
to Relative GND
[3]
..–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State
[3]
................................. –0.5 V to V
CC
+ 0.5 V
DC Input Voltage
[3]
............................. –0.5 V to V
CC
+ 0.5 V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
C
to +70
C
–40
C
to +85
C
V
CC
3.3 V
0.3 V
DC Electrical Characteristics
(Over the Operating Range)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
Automatic CE Power-down
Current —TTL Inputs
Automatic CE Power-down
Current —CMOS Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= max, f = f
max
= 1/t
RC
Commercial
Industrial
CE
2
< V
IL,
Max V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
max
CE
2
< 0.3 V, Max V
CC
,
CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V,
or V
IN
< 0.3 V, f = 0
Commercial/
Industrial
Test Conditions
I
OH
= –4.0 mA
I
OL
= 8.0 mA
–10
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
275
275
70
50
Unit
V
V
V
V
A
A
mA
mA
mA
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz, V
CC
= 3.3 V
TSOP II
6
8
FBGA
8
10
Unit
pF
pF
AC Test Loads and Waveforms
[5]
50
OUTPUT
Z
0
= 50
V
TH
= 1.5 V
30 pF* * Capacitive Load consists of all
components of the test environment.
ALL INPUT PULSES
90%
10%
90%
10%
Fall time:
> 1 V/ns
3.3 V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(b)
R2
351
R1 317
(a)
3.3 V
GND
Rise time > 1 V/ns
(c)
Notes
3. V
IL
(min) = –2.0 V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0 V). As soon as 1 ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0 V) voltage.
Document #: 38-05256 Rev. *K
Page 4 of 14
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CY7C1061AV33
AC Switching Characteristics
(Over the Operating Range)
[6]
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE
1
LOW/CE
2
HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z
[8]
WE LOW to High Z
[8]
Byte Enable to End of Write
10
7
7
0
0
7
5.5
0
3
–
7
–
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
(typical) to the first access
[7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW/CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[8]
CE
1
LOW/CE
2
HIGH to Low Z
[8]
CE
1
HIGH/CE
2
LOW to High Z
[8]
CE
1
LOW/CE
2
HIGH to Power Up
[9]
CE
1
HIGH/CE
2
LOW to Power Down
[9]
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
1
10
–
3
–
–
1
–
3
–
0
–
–
1
–
–
–
10
–
10
5
–
5
–
5
–
10
5
–
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
–10
Min
Max
Unit
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OL
/I
OH
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the
AC Test Loads and Waveforms
[5]
on page 4,
unless
specified otherwise.
7. This part has a voltage regulator that steps down the voltage from 3 V to 2 V internally. t
power
time must be provided initially before a Read/Write operation is started.
8. t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
and t
LZOE
, t
LZCE
, t
\LZWE
, t
LZBE
are specified with a load capacitance of 5 pF as in (b) of
AC Test Loads and Waveforms
[5]
on page 4.
Transition is measured
200
mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE
1
LOW (CE
2
HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading
edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
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