CY7C1250KV18-450BZXC datasheet, PDF

Datasheet> All Categories > CY7C1250KV18-450BZXC

CY7C1250KV18-450BZXC: Description36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); File Size631KB，28 Pages; ManufacturerCypress Semiconductor

Download Datasheet View All

CY7C1250KV18-450BZXC Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	CY7C1250KV18-450BZXC	-	-	View	Buy Now

CY7C1250KV18-450BZXC Overview

36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

Preview

Download Datasheet

View All

CY7C1246KV18, CY7C1257KV18

CY7C1248KV18, CY7C1250KV18

36-Mbit DDR II+ SRAM 2-Word Burst

Architecture (2.0 Cycle Read Latency)

36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

Features

■

Configurations

With Read Cycle Latency of 2.0 Cycles:

CY7C1246KV18 – 4 M × 8

CY7C1257KV18 – 4 M × 9

CY7C1248KV18 – 2 M × 18

CY7C1250KV18 – 1 M × 36

36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)

450 MHz clock for high bandwidth

2-word burst for reducing address bus frequency

Double data rate (DDR) interfaces

(data transferred at 900 MHz) at 450 MHz

Available in 2.0 clock cycle latency

Two input clocks (K and K) for precise DDR timing

❐

SRAM uses rising edges only

Echo clocks (CQ and CQ) simplify data capture in high speed

systems

Data valid pin (QVLD) to indicate valid data on the output

Synchronous internally self-timed writes

DDR II+ operates with 2.0 cycle read latency when DOFF is

asserted HIGH

Operates similar to DDR I device with 1 cycle read latency when

DOFF is asserted LOW

Core V

= 1.8 V ± 0.1 V; I/O V

DDQ

= 1.4 V to V

DD[1]

❐

Supports both 1.5 V and 1.8 V I/O supply

HSTL inputs and variable drive HSTL output buffers

Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

Offered in both Pb-free and non Pb-free packages

JTAG 1149.1 compatible test access port

Phase-locked loop (PLL) for accurate data placement

Description

Functional Description

The CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and

CY7C1250KV18 are 1.8 V synchronous pipelined SRAMs

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1246KV18), 9-bit words (CY7C1257KV18), 18-bit

words (CY7C1248KV18), or 36-bit words (CY7C1250KV18) that

burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■

Table 1. Selection Guide

450 MHz

450

×8

×9

× 18

× 36

590

600

760

400 MHz

400

540

550

690

375 MHz

375

520

530

660

333 MHz

333

480

490

600

Unit

MHz

Maximum operating frequency

Maximum operating current

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

DDQ

= 1.4 V to V

Cypress Semiconductor Corporation

Document Number: 001-57834 Rev. *B

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised February 24, 2011

[+] Feedback

Recommended Resources

HT-691/HT-694/HT-611/HT-614/HT-651/HT-658 Electric line-e

Pulse forming circuit and its waveform

Non-polar charger

Nokia 8210 mobile phone travel charger circuit

Slow start integrated regulated power supply circuit

Class B push-pull power amplifier circuit (DEPP circuit)

The difference between USB flash drives and solid-state drives (transferred): [font=SimSun][size=6][size=14px]The difference between SSD and USB flash drive, first, the main control algorithm is different, the speed of SSD is dozens of times higher than that of USB flash drive....; 白丁 Integrated technical exchanges

What basic knowledge is needed to develop router software?: I applied for a job at a company that makes routers. I want to know what basic knowledge I need to develop in this field?...; wjl506 Embedded System

Errors 1033 and 1041 occurred during Win CE6.0 customization: 1\cepcstrings.pbcxml"). D:\WINCE600\platform\ICOP_eBox4300_60DS\catalog\1041\cepcstrings.pbcxml 0 0 Error 2 Catalog Id "StringTable:MS:Cepc:1041" duplicated in files "D:\WINCE600\platform\CEPC\catalog...; jiuzhouliujun Embedded System

Let's discuss a topic that has not been mentioned in this forum - oscilloscope batteries: I used an oscilloscope to observe a small signal these days and found that there was power frequency interference. After analysis, I found that it can only be eliminated by using a battery. I asked ab...; xcuresme Test/Measurement

MSP430F149 Circuit Connection: I have two input control signals and want to send them to msp430f149 as output control signals through UART. How should I connect the circuit? Thank you very much......; yanyaqi88 Microcontroller MCU

The latest development of electronic devices (IGBT modules): [color=#1919f8]1. High-power Trench Gate IGBT Module[/color] The IGBT cells in today's high-power IGBT modules usually use trench gate IGBTs. Compared with the planar gate structure, the trench gate s...; guangqiji PCB Design

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components