CY7C1513JV18
CY7C1515JV18
72-Mbit QDR
®
II SRAM 4-Word
Burst Architecture
Features
■
Configurations
CY7C1513JV18 – 4M x 18
CY7C1515JV18 – 2M x 36
Separate independent Read and Write Data Ports
❐
Supports concurrent transactions
300 MHz clock for High Bandwidth
4-word Burst for reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 600 MHz) at 300 MHz
Two Input Clocks (K and K) for precise DDR Timing
❐
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time Mismatches
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Single multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
Separate Port Selects for Depth Expansion
Synchronous Internally Self-timed Writes
QDR
®
II operates with 1.5 Cycle Read Latency when the Delay
Lock Loop (DLL) is enabled
Operates similar to a QDR I Device with one Cycle Read
Latency in DLL Off Mode
Available in x18, and x36 Configurations
Full Data Coherency, providing Most Current Data
Core V
DD
= 1.8 (± 0.1V); IO V
DDQ
= 1.4V to V
DD
Available in 165-ball FBGA Package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
Variable Drive HSTL Output Buffers
JTAG 1149.1 compatible Test Access Port
Delay Lock Loop (DLL) for accurate data placement
■
■
■
■
Functional Description
The CY7C1513JV18, and CY7C1515JV18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR II archi-
tecture. QDR II architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words (CY7C1513JV18), or 36-bit words (CY7C1515JV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K and C and C), memory bandwidth is maximized
while simplifying system design by eliminating bus ‘turnarounds’.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x18
x36
300 MHz
300
1115
1140
250 MHz
250
865
1040
167 MHz
167
615
725
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-12560 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 24, 2009
[+] Feedback
CY7C1513JV18
CY7C1515JV18
Logic Block Diagram (CY7C1513JV18)
D
[17:0]
18
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
20
A
(19:0)
1M x 18 Array
1M x 18 Array
1M x 18 Array
1M x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
72
V
REF
WPS
BWS
[1:0]
36
Control
Logic
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
Logic Block Diagram (CY7C1515JV18)
D
[35:0]
36
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
19
A
(18:0)
512K x 36 Array
512K x 36 Array
512K x 36 Array
512K x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
144
V
REF
WPS
BWS
[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
Document Number: 001-12560 Rev. *F
Page 2 of 24
[+] Feedback
CY7C1513JV18
CY7C1515JV18
Pin Configuration
The pin configuration for CY7C1513JV18 and CY7C1515JV18 follow.
[1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1513JV18 (4M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1515JV18 (2M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC/288M
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
A
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Note
1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-12560 Rev. *F
Page 3 of 24
[+] Feedback
CY7C1513JV18
CY7C1515JV18
Pin Definitions
Pin Name
D
[x:0]
I/O
Pin Description
Input-
Data Input Signals.
Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C1513JV18
−
D
[17:0]
CY7C1515JV18
−
D
[35:0]
Input-
Write Port Select
−
Active LOW.
Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
Input-
Byte Write Select 0, 1, 2, and 3
−
Active LOW.
Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1513JV18
−
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1515JV18
−
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,
BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Input-
Address Inputs.
Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4M x 18 (4 arrays each of 1M x 18) for CY7C1513JV18 and 2M x 36 (4 arrays each of 512K x 36) for
CY7C1515JV18. Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1513JV18 and 19 address inputs for CY7C1515JV18. These inputs are ignored when the appro-
priate port is deselected.
Outputs-
Data Output Signals.
These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in
single clock mode. On deselecting the read port, Q
[x:0]
are automatically tristated.
CY7C1513JV18
−
Q
[17:0]
CY7C1515JV18
−
Q
[35:0]
Input-
Read Port Select
−
Active LOW.
Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
C clock. Each read access consists of a burst of four sequential transfers.
Input Clock
Positive Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See
Application Example
on page 8 for further details.
Negative Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See
Application Example
on page 8 for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
when in single clock mode.
CQ is Referenced with Respect to C.
This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the
Switching Characteristics
on page 20.
CQ is Referenced with Respect to C.
This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the
Switching Characteristics
on page 20.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
WPS
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
Q
[x:0]
RPS
C
C
Input Clock
K
Input Clock
K
CQ
Input Clock
Echo Clock
CQ
Echo Clock
ZQ
Input
Document Number: 001-12560 Rev. *F
Page 4 of 24
[+] Feedback
CY7C1513JV18
CY7C1515JV18
Pin Definitions
Pin Name
DOFF
I/O
Input
(continued)
Pin Description
DLL Turn Off
−
Active LOW.
Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin is connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with QDR I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Ground for the Device.
TDO
TCK
TDI
TMS
NC
Output
Input
Input
Input
N/A
N/A
N/A
Input-
Reference
Ground
NC/144M
NC/288M
V
REF
V
DD
V
SS
V
DDQ
Power Supply
Power Supply Inputs to the Core of the Device.
Power Supply
Power Supply Inputs for the Outputs of the Device.
Document Number: 001-12560 Rev. *F
Page 5 of 24
[+] Feedback
Power technology
京公网安备 11010802033920号
EEWORLD
