CY7C1526JV18-167BZI datasheet, PDF

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CY7C1526JV18-167BZI: Description72-Mbit QDR-II SRAM 4-Word Burst Architecture; File Size903KB，24 Pages; ManufacturerCypress Semiconductor

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CY7C1526JV18-167BZI Overview

72-Mbit QDR-II SRAM 4-Word Burst Architecture

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CY7C1513JV18

CY7C1515JV18

72-Mbit QDR

II SRAM 4-Word

Burst Architecture

Features

■

Configurations

CY7C1513JV18 – 4M x 18

CY7C1515JV18 – 2M x 36

Separate independent Read and Write Data Ports

❐

Supports concurrent transactions

300 MHz clock for High Bandwidth

4-word Burst for reducing Address Bus Frequency

Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 600 MHz) at 300 MHz

Two Input Clocks (K and K) for precise DDR Timing

❐

SRAM uses rising edges only

Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time Mismatches

Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

Single multiplexed Address Input Bus latches Address Inputs

for Read and Write Ports

Separate Port Selects for Depth Expansion

Synchronous Internally Self-timed Writes

QDR

II operates with 1.5 Cycle Read Latency when the Delay

Lock Loop (DLL) is enabled

Operates similar to a QDR I Device with one Cycle Read

Latency in DLL Off Mode

Available in x18, and x36 Configurations

Full Data Coherency, providing Most Current Data

Core V

= 1.8 (± 0.1V); IO V

DDQ

= 1.4V to V

Available in 165-ball FBGA Package (15 x 17 x 1.4 mm)

Offered in both Pb-free and non Pb-free Packages

Variable Drive HSTL Output Buffers

JTAG 1149.1 compatible Test Access Port

Delay Lock Loop (DLL) for accurate data placement

■

Functional Description

The CY7C1513JV18, and CY7C1515JV18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR II archi-

tecture. QDR II architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus that exists with common I/O devices. Each port is

accessed through a common address bus. Addresses for read

and write addresses are latched on alternate rising edges of the

input (K) clock. Accesses to the QDR II read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 18-bit

words (CY7C1513JV18), or 36-bit words (CY7C1515JV18) that

burst sequentially into or out of the device. Because data is trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K and C and C), memory bandwidth is maximized

while simplifying system design by eliminating bus ‘turnarounds’.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■

Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

x18

x36

300 MHz

300

1115

1140

250 MHz

250

865

1040

167 MHz

167

615

725

Unit

MHz

Cypress Semiconductor Corporation

Document Number: 001-12560 Rev. *F

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised August 24, 2009

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