CY7C1522JV18, CY7C1529JV18
CY7C1523JV18, CY7C1524JV18
72-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Features
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Functional Description
The CY7C1522JV18, CY7C1529JV18, CY7C1523JV18, and
CY7C1524JV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Double Data Rate Separate I/O (DDR-II SIO)
architecture. The DDR-II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR-II
SIO has separate data inputs and data outputs to eliminate the
need to ‘turnaround’ the data bus required with common I/O
devices. Access to each port is accomplished through a common
address bus. Addresses for read and write are latched on
alternate rising edges of the input (K) clock. Write data is regis-
tered on the rising edges of both K and K. Read data is driven on
the rising edges of C and C if provided, or on the rising edge of
K and K if C/C are not provided. Each address location is
associated with two 8-bit words in the case of CY7C1522JV18,
two 9-bit words in the case of CY7C1529JV18, two 18-bit words
in the case of CY7C1523JV18, and two 36-bit words in the case
of CY7C1524JV18 that burst sequentially into or out of the
device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
300 MHz Clock for High Bandwidth
2-word Burst for reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces
(data transferred at 600 MHz) at 300 MHz
Two Input Clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two Input Clocks for output data (C and C) to minimize Clock
Skew and Flight Time mismatches
Echo Clocks (CQ and CQ) Simplify Data Capture in High Speed
Systems
Synchronous Internally Self-timed Writes
DDR-II operates with 1.5 Cycle Read Latency when the Delay
Lock Loop (DLL) is enabled
Operates similar to a DDR-I device with 1 Cycle Read Latency
in DLL Off Mode
1.8V Core Power Supply with HSTL inputs and outputs
Variable drive HSTL Output Buffers
Expanded HSTL Output Voltage (1.4V–V
DD
)
Available in 165-Ball FBGA Package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 Compatible Test Access Port
Delay Lock Loop (DLL) for Accurate Data Placement
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Configurations
CY7C1522JV18 – 8M x 8
CY7C1529JV18 – 8M x 9
CY7C1523JV18 – 4M x 18
CY7C1524JV18 – 2M x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
300 MHz
300
900
900
950
1080
250 MHz
250
800
800
800
900
Unit
MHz
mA
Cypress Semiconductor Corporation
Document #: 001-44700 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 31, 2009
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