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530EB212M500DGR

Description
XO, Clock, 10MHz Min, 945MHz Max, 212.5MHz Nom
CategoryPassive components    oscillator   
File Size1MB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530EB212M500DGR Overview

XO, Clock, 10MHz Min, 945MHz Max, 212.5MHz Nom

530EB212M500DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid1148368951
package instructionDILCC6,.2
Reach Compliance Codeunknown
Other featuresTRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee3
Installation featuresSURFACE MOUNT
Number of terminals6
Nominal operating frequency212.5 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
Output load50 OHM
Maximum output low current32 mA
Encapsulate equivalent codeDILCC6,.2
physical size7.0mm x 5.0mm x 1.8mm
power supply2.5 V
Certification statusNot Qualified
longest rise time0.35 ns
Maximum slew rate121 mA
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceMatte Tin (Sn)
S i 5 3 0 / 5 31
R
EVISION
D
C
R YS TA L
O
SCILLATOR
(XO) (10 M H
Z T O
1 . 4 GH
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
1
6
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
OE
2
5
CLK–
GND
3
4
CLK+
Si530 (LVDS/LVPECL/CML)
OE
1
6
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
2
5
NC
GND
3
4
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
1
6
V
DD
NC
2
5
CLK–
GND
3
4
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.4 5/13
Copyright © 2013 by Silicon Laboratories
Si530/531
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