564AAJA002160ABG datasheet, PDF

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564AAJA002160ABG: DescriptionLVPECL Output Clock Oscillator,; CategoryPassive components oscillator; File Size1MB，35 Pages; ManufacturerSilicon Laboratories Inc

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564AAJA002160ABG Overview

LVPECL Output Clock Oscillator,

564AAJA002160ABG Parametric

Parameter Name	Attribute value
Objectid	8363003713
Reach Compliance Code	unknown
Other features	TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; DIFFERENTIAL OUTPUT; 2.5V AVAILABLE
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Installation features	SURFACE MOUNT
Number of terminals	8
Maximum operating frequency	3000 MHz
Minimum operating frequency	0.2 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
Output load	50 OHM
Encapsulate equivalent code	DILCC8,.2
physical size	7mm x 5mm x 1.33mm
longest rise time	0.35 ns
Maximum slew rate	160 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

564AAJA002160ABG Preview

Ultra Series

™

Crystal Oscillator

Si564 Data Sheet

Ultra Low Jitter I2C Programmable XO (90 fs), 0.2 to

3000 MHz

The Si564 Ultra Series

™

oscillator utilizes Silicon Laboratories’ advanced 4

generation DSPLL

technology to provide an ultra-low jitter, low phase noise

clock at any output frequency. The device is user-programmed via simple

I2C commands to provide any frequency from 0.2 to 3000 MHz with <1 ppb

resolution and maintains exceptionally low jitter for both integer and fraction-

al frequencies across its operating range. The Si564 offers excellent reliabili-

ty and frequency stability as well as guaranteed aging performance. On-chip

power supply filtering provides industry-leading power supply noise rejection,

simplifying the task of generating low jitter clocks in noisy systems that use

switched-mode power supplies. The Si564 has a dramatically simplified sup-

ply chain that enables Silicon Labs to ship custom frequency samples 1-2

weeks after receipt of order. Unlike a traditional XO, where a different crystal

is required for each output frequency, the Si564 uses one simple crystal and

a DSPLL IC-based approach to provide the desired output frequency. The

Si564 is factory-configurable for a wide variety of user specifications, includ-

ing startup frequency, I2C address, output format, and OE pin location/

polarity. Specific configurations are factory-programmed at time of shipment,

eliminating the long lead times associated with custom oscillators.

Pin Assignments

SDA

OE/FS/NC

VDD

KEY FEATURES

• I2C programmable to any frequency from 0.2 to

3000 MHz with < 1 ppb resolution

• Ultra low jitter: 90 fs RMS Typ (12 kHz – 20 MHz)

• Configure up to 4 pin-selectable startup frequencies

• I2C interface supports 100 kbps, 400 kbps, and 1

Mbps (Fast Mode Plus)

• Excellent PSRR and supply noise immunity: –80

dBc Typ

• 3.3 V, 2.5 V and 1.8 V V

supply operation from

the same part number

• LVPECL, LVDS, CML, HCSL, CMOS, and Dual

CMOS output options

• 3.2x5, 5x7 mm package footprints

• Samples available with 1-2 week lead times

APPLICATIONS

• 100G/200G/400G OTN, coherent optics, PAM4

• 10G/40G/100G optical ethernet

• 3G-SDI/12G-SDI/24G-SDI broadcast video

• Servers, switches, storage, search acceleration

• Test and measurement

• FPGA/ASIC clocking

NC/OE/FS

GND

SCL

(Top View)

CLK–

CLK+

silabs.com

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Rev. 1.0

Pin #

1, 2

Descriptions

Selectable via ordering option

OE = Output enable; FS = Frequency Select; NC = No connect

GND = Ground

CLK+ = Clock output

CLK- = Complementary clock output. Not used for CMOS.

VDD = Power supply

SDA = I2C Serial Data

SCL = I2C Serial Clock

NVM

Control

OSC

Fixed

Frequency

Crystal

Frequency

Flexible

DSPLL

DCO

Low

Noise

Driver

Digital

Phase

Detector

Phase Error

Cancellation

Phase Error

Fractional

Divider

Digital

Loop

Filter

Flexible

Formats,

1.8V – 3.3V

Operation

Power Supply Regulation

OE, Frequency Select

(I2C and Pin Control)

Built-in Power Supply

Noise Rejection

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Rev. 1.0

Si564 Data Sheet

Ordering Guide

1. Ordering Guide

The Si564 XO supports a variety of options including startup frequency, output format, and OE pin location/polarity, as shown in the

chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks.

Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to

www.silabs.com/oscillators

access this tool and for further ordering instructions.

XO Series

564

Description

I2C Oscillator

Temp Stability

Total Stability

Package

5x7 mm

3.2x5 mm

Temperature Grade

-40 to 85 °C

20 ppm

50 ppm

564

Device Revision

Signal Format

LVPECL

LVDS

CMOS

CML

HCSL

Dual CMOS

(In-Phase)

Dual CMOS

(Complementary)

Custom

Order

Option

2.5, 3.3 V

1.8, 2.5, 3.3 V

VDD Range

1.8, 2.5, 3.3 V

Code

OE Pin

Pin 1

Pin 2

Pin 1

Pin 2

Code

Supported Frequency Range

0.2-3000 MHz

0.2-1500 MHz

0.2-800 MHz

0.2-325 MHz (CMOS available to 250 MHz)

Pinout Option

OE Polarity

Active High

Active Low

Active High

Active Low

Active High

Active Low

Active High

Active Low

FS0

(Dual)

Pin 2

Pin 1

FS1

(Quad)

Pin 2

Frequency

Code

<Blank>

Reel

Tape and Reel

Coil Tape

Description

The Si564 supports one,

two, or four user-defined

startup frequencies in the

range selected by the

Supported Frequency

Range code. A user-

defined 7-bit I2C address

is supported. Each unique

startup configuration and

I2C address combination

is assigned a 6-digit code.

xxxxxx

Single

Codes A, B

SDA

GND

VDD

CLK–

CLK+

FS0

GND

Dual

Codes E, F

SDA

VDD

CLK–

CLK+

FS0

FS1

GND

Quad

Code J

SDA

VDD

CLK–

CLK+

SCL

Codes C, D

SDA

GND

VDD

CLK–

CLK+

FS0

GND

Codes G, H

SDA

VDD

CLK–

CLK+

SCL

If replacing Si570A-K, use Code C

If replacing Si570M-W, use Code D

Notes:

1. Contact Silicon Labs for non-standard configurations.

2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.

3. Create custom part numbers at

www.silabs.com/oscillators.

silabs.com

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Rev. 1.0 | 3

Si564 Data Sheet

Ordering Guide

1.1 Technical Support

Frequently Asked Questions (FAQ)

Oscillator Phase Noise Lookup Utility

Quality and Reliability

Development Kits

www.silabs.com/Si564-FAQ

www.silabs.com/oscillator-phase-noise-lookup

www.silabs.com/quality

www.silabs.com/oscillator-tools

silabs.com

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Rev. 1.0 | 4

Si564 Data Sheet

Electrical Specifications

2. Electrical Specifications

Table 2.1. Electrical Specifications

= 1.8 V, 2.5 or 3.3 V ± 5%, T

= –40 to 85 ºC

Parameter

Temperature Range

Frequency Range

Symbol

CLK

LVPECL, LVDS, CML

HCSL

CMOS, Dual CMOS

Supply Voltage

3.3 V

2.5 V

1.8 V

Supply Current

LVPECL (output enabled)

LVDS/CML (output enabled)

HCSL (output enabled)

CMOS (output enabled)

Dual CMOS (output enabled)

Tristate Hi-Z (output disabled)

Temperature Stability

Total Stability

Rise/Fall Time

(20% to 80% V

)

STAB

Frequency stability Grade A

LVPECL/LVDS/CML

CMOS / Dual CMOS

= 5 pF)

HCSL, F

CLK

>50 MHz

Duty Cycle

Output Enable (OE),

Frequency Select (FS0, FS1)

Powerup Time

LVPECL Output Option

OSC

Output Disable Time, F

CLK

>10 MHz

Output Enable Time, F

CLK

>10 MHz

Settling Time after FS Change

Time from 0.9 × V

until output fre-

quency (F

CLK

) within spec

Mid-level

Swing (diff, F

CLK

< 1.5 GHz)

Swing (diff, F

CLK

> 1.5 GHz)

All formats

Test Condition/Comment

Min

–40

0.2

3.135

2.375

1.71

—

–20

–50

—

0.7 × V

—

– 1.42

1.1

0.55

Typ

—

3.3

2.5

1.8

110

—

0.5

—

Max

3000

400

250

3.465

2.625

1.89

160

157

130

135

145

—

350

1.5

550

—

0.3 × V

– 1.25

1.9

1.7

Unit

ºC

MHz

ppm

µs

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Rev. 1.0 | 5

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