April 1998
ML4812*
Power Factor Controller
GENERAL DESCRIPTION
The ML4812 is designed to optimally facilitate a peak
current control boost type power factor correction system.
Special care has been taken in the design of the ML4812
to increase system noise immunity. The circuit includes a
precision reference, gain modulator, error amplifier, over-
voltage protection, ramp compensation, as well as a high
current output. In addition, start-up is simplified by an
under-voltage lockout circuit with 6V hysteresis.
In a typical application, the ML4812 functions as a
current mode regulator. The current which is necessary to
terminate the cycle is a product of the sinusoidal line
voltage times the output of the error amplifier which is
regulating the output DC voltage. Ramp compensation is
programmable with an external resistor, to provide stable
operation when the duty cycle exceeds 50%.
FEATURES
s
s
Precision buffered 5V reference (±0.5%)
Current-input gain modulator reduces external
components and improves noise immunity
Programmable ramp compensation circuit
1A peak current totem-pole output drive
Overvoltage comparator helps prevent output
voltage “runaway”
Wide common mode range in current sense
comparators for better noise immunity
Large oscillator amplitude for better noise immunity
s
s
s
s
s
* Some Packages Are End Of Life
BLOCK DIAGRAM
(Pin Configuration Shown is for DIP Version)
OVP
5
+
SHDN
S
+
–
–
5V
1
–
Q
Q
10
ISENSE
5V
VCC
OUT
12
R
2
3
GM OUT
EA OUT
ERROR
AMP
UNDER
VOLTAGE
LOCKOUT
IEA
PWR GND
11
VREF
VCC
4
EA–
5V
14
13
+
–
32V
6
ISINE
GAIN MODULATOR
GND
15
7
16
RAMP COMP
CT
5V
CLOCK
9
8
RT
OSC
1kΩ
1
ML4812
PIN CONFIGURATION
ML4812
16-Pin PDIP (P16)
ISENSE
GM OUT
EA OUT
EA–
OVP
ISINE
RAMP COMP
RT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CT
GND
VREF
VCC
OUT
PWR GND
SHDN
CLOCK
EA OUT
EA–
NC
OVP
ISINE
4
5
6
7
8
9 10 11 12 13
ML4812
20-Pin PLCC (Q20)
GM OUT
ISENSE
GND
NC
3
2
1 20 19
18
17
16
15
14
VREF
VCC
NC
OUT
PWR GND
RAMP COMP
CLOCK
CT
TOP VIEW
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
I
SENSE
Input from the current sense
transformer to the non-inverting input
of the PWM comparator.
Output of gain modulator.
A resistor to ground on this pin
converts the current to a voltage.
This pin is clamped to 5V and tied
to the inverting input of the PWM
comparator.
Output of error amplifier.
Inverting input to error amplifier.
Input to over voltage comparator.
Current gain modulator input.
Buffered output from the oscillator
ramp (C
T
). A resistor to ground sets the
current which is internally subtracted
from the product of I
SINE
and I
EA
in
the gain modulator.
8
R
T
2
GM OUT
Oscillator timing resistor pin. A 5V
source sets a current in the external
resistor which is mirrored to charge
C
T
.
Digital clock output.
A TTL compatible low level on this
pin turns off the output.
9
10
11
CLOCK
SHDN
3
4
5
6
7
EA OUT
EA–
OVP
I
SINE
RAMP
COMP
PWR GND Return for the high current totem pole
output.
OUT
V
CC
V
REF
GND
C
T
High current totem pole output.
Positive Supply for the IC.
Buffered output for the 5V voltage
reference.
Analog signal ground.
Timing capacitor for the oscillator.
12
13
14
15
16
2
SHDN
NC
RT
ML4812
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.
Supply Current (I
CC
) ............................................... 30mA
Output Current Source or Sink (OUT) DC ................ 1.0A
Output Energy (capacitive load per cycle) .................. 5µJ
Gain Modulator I
SINE
Input (I
SINE
) ......................... 1.2mA
Error Amp Sink Current (EA OUT) .......................... 10mA
Oscillator Charge Current ........................................ 2mA
Analog Inputs (I
SENSE
, EA–, OVP) .............. –0.3V to 5.5V
Junction Temperature ............................................. 150°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (soldering 10 sec.) ..................... 260°C
Thermal Resistance (θ
JA
)
20-Pin PLCC .................................................... 60°C/W
16-Pin PDIP ..................................................... 65°C/W
OPERATING CONDITIONS
Temperature Range
ML4812CX ............................................... 0°C to 70°C
ML4812IX ............................................. –40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
CC
= 15V , R
T
= 14kΩ, C
T
= 1000pF, T
A
= Operating Temperature Range (Notes 1, 2).
PARAMETER
OSCILLATOR
Initial Accuracy
Voltage Stability
Temperature Stability
Total Variation
Ramp Valley to Peak
R
T
Voltage
Discharge Current (R
T
open)
Clock Out Voltage Low
Clock Out Voltage High
REFERENCE
Output Voltage
Line Regulation
Load Regulation
Temperature Stability
Total Variation
Output Noise Voltage
Long Term Stability
Short Circuit Current
ERROR AMPLIFIER
Input Offset Voltage
Input Bias Current
Open Loop Gain
PSRR
Output Sink Current
Output Source Current
Output High Voltage
Output Low Voltage
Unity Gain Bandwidth
1 < V
EA OUT
< 5V
12V < V
CC
< 25V
V
EA OUT
= 1.1V, V
EA–
= 6.2V
V
EA OUT
= 5.0V, V
EA–
= 4.8V
I
EA OUT
= –0.5mA, V
EA–
= 4.8V
I
EA OUT
= 1mA, V
EA–
= 6.2V
60
60
2
–0.5
5.3
–0.1
75
75
12
–1.0
5.5
0.5
1.0
1.0
±15
–1.0
mV
µA
dB
dB
mA
mA
V
V
MHz
Line, load, temp.
10Hz to 10kHz
T
J
= 125°C, 1000 hours
V
REF
= 0V
–30
4.9
50
5
–85
25
–180
T
J
= 25°C, I
O
= 1mA
12V < V
CC
< 25V
1mA < I
O
< 20mA
4.95
5.00
2
2
0.4
5.1
5.05
20
20
V
mV
mV
%
V
µV
mV
mA
T
J
= 25°C, V
CT
= 2V
V
CT
= 2V
R
L
= 16kΩ
R
L
= 16kΩ
3.0
4.8
7.8
7.3
Line, temperature
90
3.3
5.0
8.4
8.4
0.2
3.5
5.2
9.0
9.3
0.5
T
J
= 25°C
12V < V
CC
< 18V
91
98
0.3
2
108
105
kHz
%
%
kHz
V
V
mA
mA
V
V
CONDITIONS
MIN
TYP
MAX
UNITS
3
ML4812
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
GAIN MODULATOR
I
SINE
Input Voltage
Output Current (GM OUT)
I
SINE
= 500µA
I
SINE
= 500µA, EA– = V
REF
–20mV
I
SINE
= 500µA, EA– = V
REF
+ 20mV
I
SINE
= 1mA, EA– = V
REF
– 20mV
I
SINE
= 500µA, EA– = V
REF
– 20mV,
I
RAMP COMP
= 50µA
Bandwidth
PSRR
OVP COMPARATOR
Input Offset Voltage
Hysteresis
Input Bias Current
Propagation Delay
PWM COMPARATOR: I
SENSE
Input Offset Voltage
Input Offset Current
Input Common Mode Range
Input Bias Current
Propagation Delay
I
LIMIT
Trip Point
OUTPUT
Output Voltage Low
I
OUT
= –20mA
I
OUT
= –200mA
Output Voltage High
I
OUT
= 20mA
I
OUT
= 200mA
Output Voltage Low in UVLO
Output Rise/Fall Time
Shutdown
I
OUT
= –5mA, V
CC
= 8V
C
L
= 1000pF
V
IH
V
IL
I
IL
, V
SHDN
= 0V
I
IH
, V
SHDN
= 5V
UNDER-VOLTAGE LOCKOUT
Startup Threshold
Shutdown Threshold
V
REF
Good Threshold
SUPPLY
Supply Current
Start-Up, V
CC
= 14V, T
J
= 25°C
Operating, T
J
= 25°C
Internal Shunt Zener Voltage
I
CC
= 30mA
25
0.8
20
30
1.2
25
34
mA
mA
V
15
9
16
10
4.4
17
11
V
V
V
2.0
0.8
–1.5
10
13
12
0.1
1.6
13.5
13.4
0.1
50
0.8
0.4
2.2
V
V
V
V
V
ns
V
V
mA
µA
V
GM OUT
= 5.5V
4.8
–0.2
–2
150
5
5.2
±15
±1
5.5
–10
mV
µA
V
µA
ns
V
Output Off
Output On
–25
95
105
–0.3
150
+5
115
–3
mV
mV
µA
ns
12V < V
CC
< 25V
860
0.4
430
0.7
470
3
940
455
200
70
0.9
510
10
1020
V
µA
µA
µA
µA
kHz
dB
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2:
V
CC
is raised above the Startup Threshold first to activate the IC, then returned to 15V.
4
ML4812
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4812 oscillator charges the external capacitor (C
T
)
with a current (I
SET
) equal to 5/R
SET
. When the capacitor
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
Q2 provides a high pulse.
The Oscillator period can be described by the following
relationship:
T
OSC
=
T
RAMP
+
T
DEADTIME
where:
V
OUT
=
V
IN
1
-
D
ON
C
T
´
V
RAM P VALLEY TO PEAK
8.4mA
-
I
SET
and:
T
DEADTIM E
=
10
8
10nF
EXTERNAL
CLOCK
CSYNC
10
90%
5nF
2nF
1nF
85%
MAXIMUM DUTY CYCLE (%)
5
80%
SYNC
Q
2
RT
9
RT (kΩ)
3
70%
20nF
2
ISET
RSYNC
RT
16
CT
8.4mA
ISET
+
CT
1
10
100
OSCILLATOR FREQUENCY (kHz)
1000
5.6V
-
Q
1
Figure 2. Oscillator Timing Resistance vs. Frequency
15
OUTPUT SATURATION VOLTAGE (V)
CLOCK
tD
RAMP PEAK
V(CT)
RAMP VALLEY
VCC
14
13
VCC = 15V
80µs PULSED LOAD
120Hz RATE
SOURCE SATURATION
LOAD TO GROUND
SINK SATURATION
LOAD TO VCC
3
2
1
Figure 1. Oscillator Block Diagram
GND
0
0
200
400
600
800
OUTPUT CURRENT (mA)
Figure 3. Output Saturation Voltage vs. Output Current
5
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