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ACEX1: DescriptionProgrammable Logic Device Family; File Size364KB，86 Pages; ManufacturerETC

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ACEX1 Overview

Programmable Logic Device Family

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ACEX 1K

Programmable Logic Device Family

Data Sheet

September 2001, ver. 3.3

Features...

Programmable logic devices (PLDs), providing low cost

system-on-a-programmable-chip (SOPC) integration in a single

device

–

Enhanced embedded array for implementing megafunctions

such as efficient memory and specialized logic functions

–

Dual-port capability with up to 16-bit width per embedded array

block (EAB)

–

Logic array for general logic functions

High density

–

10,000 to 100,000 typical gates (see

Table 1)

–

Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be

used without reducing logic capacity)

Cost-efficient programmable architecture for high-volume

applications

–

Cost-optimized process

–

Low cost solution for high-performance communications

applications

System-level features

–

MultiVolt

I/O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

–

Low power consumption

–

Bidirectional I/O performance (setup time [t

] and clock-to-

output delay [t

]) up to 250 MHz

–

Fully compliant with the peripheral component interconnect

Special Interest Group (PCI SIG)

PCI Local Bus Specification,

Revision 2.2

for 3.3-V operation at 33 MHz or 66 MHz

Tools

Table 1. ACEX

1K Device Features

Feature

Typical gates

Maximum system gates

Logic elements (LEs)

EABs

Total RAM bits

Maximum user I/O pins

EP1K10

10,000

56,000

576

12,288

136

EP1K30

30,000

119,000

1,728

24,576

171

EP1K50

50,000

199,000

2,880

40,960

249

EP1K100

100,000

257,000

4,992

49,152

333

Altera Corporation

A-DS-ACEX-3.3

ACEX1 Related Products

	ACEX1	EP1K10	EP1K100	EP1K30	EP1K50
Description	Programmable Logic Device Family	Programmable Logic Device Family	Programmable Logic Device Family	Programmable Logic Device Family	Programmable Logic Device Family

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