Si4022 Universal ISM Band
FSK Transmitter
DESCRIPTION
Integration’s Si4022 is a single chip, low power, multi-channel FSK
transmitter designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the bands at 868 and 915 MHz. Used in
conjunction with Integration’s FSK receivers, it is a flexible, low cost, and
highly integrated solution that does not require production alignments. All
required RF functions are integrated. Only an external crystal and bypass
filtering is needed for operation.
The transmitter has a completely integrated PLL for easy RF design, and its
rapid settling time allows for fast frequency-hopping, bypassing multipath
fading and interference to achieve robust wireless links. The PLL’s high
resolution allows the usage of multiple channels in any of the bands. In
addition, highly stable and accurate FSK modulation is accomplished by
direct closed-loop modulation with bit rates up to 115.2 kbps.
The integrated power amplifier of the transmitter has an open-collector
differential output and can directly drive a loop antenna with programmable
output level, no additional matching network is required. An automatic
antenna tuning circuit is built in to avoid both costly trimming procedures
and de-tuning due to the “hand effect”.
For battery-operated applications the device supports various power saving
modes with wake-up interrupt generation options based on a low battery
voltage detector and a sleep timer. Several additional features ease system
design. Power-on reset and clock signals are provided to the microcontroller.
An on-chip baud rate generator and a data FIFO are available. The transmitter
is programmed and controlled via an SPI compatible interface.
SDI
SCK
nSEL
SDO
nIRQ
CLK
VREFO
VSS_D
1
2
3
4
5
6
7
8
Si4022
PIN ASSIGNMENT
16
15
14
13
12
11
10
9
FSK
VDD
VSS_B
RF02
RF01
VSS_A
nRES
XTL / REF
This document refers to Si4022-IC Rev A0.
See www.silabs.com/integration for any applicable
errata. See back page for ordering information.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully integrated (low BOM, easy design-in)
No alignment required in production
Fast settling, programmable, high-resolution PLL
Fast frequency hopping capability
Stable and accurate FSK modulation with
programmable deviation
Programmable PLL loop bandwidth
Direct loop antenna drive
Automatic antenna tuning circuit
Programmable output power level
SPI bus for interfacing with microcontroller
Clock and reset signals for microcontroller
64 bit TX data FIFO
Integrated programmable crystal load capacitor
Standard 10 MHz crystal reference
Power-saving modes
Multiple event handling options for wake-up
activation
Wake-up timer
Low battery detection
2.2 to 3.8 V supply voltage
Low power consumption
Low standby current (typ. 0.3
μA)
FUNCTIONAL BLOCK DIAGRAM
XTL
9
CRYSTAL
OSCILLATOR
REFERENCE
13
RF02
RF01
SYNTHESIZER
12
CLOCK
FREQUENCY
LOAD CAP
LEVEL
6
CLK
nIRQ
SDO
SDI
SCK
nSEL
FSK
VDD
VSS_A
VDD_B
VSS_D
VREFO
15
11
LOW
BATTERY
DETECT
LOW BAT
TRESHOLD
CONTROLLER
5
4
1
2
TYPICAL APPLICATIONS
•
•
•
•
•
•
•
•
•
Remote control
Home security and alarm
Wireless keyboard/mouse and other PC peripherals
Toy control
Remote keyless entry
Tire pressure monitoring
Telemetry
Personal/patient data logging
Remote automatic meter reading
14
8
7
TIMEOUT
WAKE -UP
TIMER
3
PERIOD
16
10
nRES
1
IA4222-DS rev 1.1r 0308
www.silabs.com/integration
i
Si4022
DETAILED FEATURE-LEVEL DESCRIPTION
The Si4022 FSK transmitter is designed to cover the unlicensed
frequency bands at 868, and 915 MHz. The device facilitates
compliance with FCC and ETSI requirements.
Low Battery Voltage Detector
The low battery detector circuit monitors periodically (typ. 8 ms)
the supply voltage and generates an interrupt if it falls below a
programmable threshold level.
PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip
crystal-controlled reference oscillator. The PLL’s high resolution
allows the usage of multiple channels in any of the bands. The
FSK deviation is selectable (from 20 to 160 kHz with 20 kHz
increments) to accommodate various bandwidth, data rate and
crystal tolerance requirements, and it is also highly accurate
due to the direct closed-loop modulation of the PLL. The
transmitted digital data can be sent asynchronously through
the FSK pin or over the control interface using the appropriate
command.
The RF VCO in the PLL performs automatic calibration, which
requires only a few microseconds. To ensure proper operation
in the programmed frequency band, the RF VCO is automatically
calibrated upon activation of the synthesizer.
Wake-Up Timer
The wake-up timer has very low current consumption (4
μA
max)
and can be programmed from 1 ms to several hours.
It calibrates itself to the crystal oscillator at every startup and
then at every 40 seconds with an accuracy of ±0.5%. When the
crystal oscillator is switched off, the calibration circuit switches
it back on only long enough for a quick calibration (a few
milliseconds) to facilitate accurate wake-up timing. The periodic
autocalibration feature can be turned off.
Event Handling
In order to minimize current consumption, the transmitter
supports the sleep mode. Switching between the various modes
is controlled by the appropriate bits in the
Power Management
Command
(page 11).
Si4022 generates an interrupt signal on several events (wake-
up timer timeout, low supply voltage detection, on-chip FIFO
almost empty). This signal can be used to wake up the
microcontroller, ef fectively reducing the period the
microcontroller has to be active. The cause of the interrupt can
be read out from the receiver by the microcontroller through the
SDO pin.
RF Power Amplifier (PA)
The power amplifier has an open-collector differential output
and can directly drive a loop antenna with a programmable output
power level. An automatic antenna tuning circuit is built in to
avoid costly trimming procedures and the so-called “hand
effect.”
Crystal Oscillator and Microcontroller Clock Output
The chip has a single-pin crystal oscillator circuit, which provides
a 10 MHz reference signal for the PLL. To reduce external parts
and simplify design, the crystal load capacitor is internal and
programmable. Guidelines for selecting the appropriate crystal
can be found later in this datasheet. The transmitter can supply
the clock signal for the microcontroller, so accurate timing is
possible without the need for a second crystal. In normal
operation it is divided from the reference 10 MHz. During sleep
mode a low frequency (typical 32 kHz) output clock signal can
be switched on.
When the microcontroller turns the crystal oscillator off by
clearing the appropriate bit using the
Power Management
Command,
the chip provides a certain number (default is 128)
of further clock pulses (“clock tail”) for the microcontroller to
let it go to idle or sleep mode.
Interface and Controller
An SPI compatible serial interface lets the user select the
frequency band, center frequency of the synthesizer, and the
output power. Division ratio for the microcontroller clock, wake-
up timer period, and low supply voltage detector threshold are
also programmable. Any of these auxiliary functions can be
disabled when not needed. All parameters are set to default after
power-on; the programmed values are retained during sleep mode.
The interface supports the read-out of a status register, providing
detailed information about the status of the transmitter.
2
Si4022
PIN DEFINITION
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
SDI
SCK
nSEL
SDO
nIRQ
CLK
VREFO
VSS_D
1
2
3
4
5
6
7
8
16
15
14
FSK
VDD
VSS_B
RF02
RF01
VSS_A
nRES
XTL / REF
IA4222
13
12
11
10
9
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
SDI
SCK
nSEL
SDO
nIRQ
CLK
VREFO
VSS_D
XTL / REF
Function
SDI
SCK
nSEL
SDO
nIRQ
CLK
VREFO
VSS_D
XTL
REF
Type
DI
DI
DI
DO
DO
DO
AO
S
AIO
DI
DO
S
AO
AO
S
S
DI
Serial control / data input
Serial interface clock input
Description
Chip (interface) select input (active low)
Serial status data output
Interrupt request output (active low)
Clock output for the microcontroller
Voltage reference output
Negative supply voltage (digital)
Crystal connection (other terminal of crystal to VSS)
External reference input
Reset output (active low)
Negative supply voltage (analog)
RF differential signal output (open collector)
RF differential signal output (open collector)
Negative supply voltage (bulk)
Positive supply voltage
Data input for asynchronous modulation
nRES
VSS_A
RFO1
RFO2
VSS_B
VDD
FSK
nRES
VSS_A
RFO1
RFO2
VSS_B
VDD
FSK
3
Si4022
GENERAL DEVICE SPECIFICATION
All voltages are referenced to V
ss
, the potential on the ground reference pin VSS.
Absolute Maximum Ratings (non-operating)
Symbol
V
dd
V
in
I
in
ESD
T
st
T
ld
Parameter
Positive supply voltage
Voltage on any pin
Input current into any pin except VDD and VSS
Electrostatic discharge with human body model
Storage temperature
Lead temperature (soldering, max 10 s)
Min
-0.5
-0.5
-25
Max
6.0
V
dd
+0.5
25
1000
Units
V
V
mA
V
o
o
-55
125
260
C
C
Recommended Operating Range
Symbol
V
dd
T
op
Parameter
Positive supply voltage
Ambient operating temperature
Min
2.2
-40
Max
3.8
+85
Units
V
o
C
ELECTRICAL SPECIFICATION
(Min/max values are valid over the whole recommended operating range, typ conditions: T
op
= 27
o
C; V
dd
= V
oc
= 2.7 V)
DC Characteristics
Symbol
I
dd,TX0
I
dd,TXmax
I
pd
I
lb
I
x
V
lb
V
lba
V
POR
Parameter
Supply current
Supply current
Standby current (Note 1)
Low battery voltage detector and
wake-up timer current
Idle current
Low battery detection threshold
Low battery detection accuracy
V
dd
threshold required
to generate a POR
POR hysteresis
V
dd
slew rate
Conditions/Notes
868 MHz band, P
out
= 0dBm
915 MHz band, P
out
= 0dBm
868 MHz band, P
out
= P
max
915 MHz band, P
out
= P
max
all blocks disabled
Min
Typ
14
15
23
24
1
Max
Units
mA
mA
µA
5
crystal oscillator is ON
programmable in 0.1 V steps
2.0
± 0.05
1.5
larger glithches on the V
dd
generate a POR even above
the threshold V
POR
for proper POR generation
0.1
0.5
3.5
µA
mA
V
V
V
V
POR,hyst
SR
Vdd
0.6
V
V/ms
Note 1: Using a CR2032 battery (225 mAh capacity), the expected battery life is greater than 2 years using a 60-second wake-up period
for sending 100 bytes packets in length at 19.2 kbps with +6 dBm output power in the 915 MHz band.
4
Si4022
DC Characteristics (continued)
Symbol
V
il
V
ih
I
il
I
ih
V
ol
V
oh
Parameter
Digital input low level
Digital input high level
Digital input current
Digital input current
Digital output low level
Digital output high level
Conditions/Notes
Min
0.7*V
dd
Typ
Max
0.3*V
dd
Units
V
V
V
il
= 0 V
V
ih
= V
dd
, V
dd
= 3.8 V
I
ol
= 2 mA
I
oh
= -2 mA
-1
-1
1
1
0.4
µA
µA
V
V
V
dd
-0.4
AC Characteristics
Symbol
f
LO
f
ref
f
res
t
lock
t
sp
C
xl
t
POR
t
sx
t
PBt
t
wake-up
Parameter
Transmitter frequency
PLL reference frequency
PLL frequency resolution
PLL lock time
PLL startup time
Crystal load capacitance,
see crystal selection guide
Internal POR pulse width
(Note 2)
Crystal oscillator startup time
Wake-up timer clock period
Programmable wake-up time
Conditions/Notes
868 MHz band, 20 kHz resolution
915 MHz band, 20 kHz resolution
(Note 1)
Min
801.92
881.92
9
Typ
Max
878.06
958.06
Units
MHz
MHz
kHz
μs
10
20
11
Frequency error < 1kHz
after 1 MHz step
Initial calibration after power-up
with running crystal oscillator
Programmable in 0.5 pF steps,
tolerance +/- 10%
After V
dd
has reached 90% of
final value
Crystal ESR < 100
Ω
Calibrated every 40 seconds
(Note 3)
0.995
1
8.5
30
500
16
50
2
1
100
5
1.005
8.4*10
6
μs
pF
ms
ms
ms
ms
Note 1: Using anything but a 10 MHz crystal is allowed but not recommended because all crystal-referred timing and frequency
parameters will change accordingly.
Note 2: No command are accepted by the chip during this period.
Note 3: Autocalibration can be turned off.
5
京公网安备 11010802033920号
EEWORLD
