PIC16(L)F1782/1783
PIC16(L)F1782/1783 Family
Silicon Errata and Data Sheet Clarification
The PIC16(L)F1782/1783 family devices that you have
received conform functionally to the current Device
Data Sheet (DS41579D), except for the anomalies
described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC16(L)F1782/1783 silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2
apply to the current silicon
revision (B4).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select
Programmer >
Reconnect.
b) For MPLAB X IDE, select
Window >
Dashboard
and click the
Refresh Debug
Tool Status
icon (
).
Depending on the development tool used, the
part number
and
Device Revision ID value
appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
5.
Data Sheet clarifications and corrections start on page
10, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC16(L)F1782/
1783 silicon revisions are shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
DEVICE ID<13:0>
(1),(2)
Part Number
DEV<8:0>
REV<4:0> Silicon Revision
B2
B4
0 1000
0 1000
0 1000
0 1000
PIC16F1782
PIC16LF1782
PIC16F1783
PIC16LF1783
Note 1:
2:
01 0111 000
01 0111 001
01 0110 010
01 0111 010
0 0110
0 0110
0 0110
0 0110
The Device ID is located in the configuration memory at address 8006h.
Refer to the
“PIC16(L)F178X Memory Programming Specification”
(DS41457) for detailed information on
Device and Revision IDs for your specific device.
2012-2014 Microchip Technology Inc.
DS80000541D-page 1
PIC16(L)F1782/1783
TABLE 2:
Module
ADC
ADC
ADC
ADC
Op Amp
Comparator
Comparator
SILICON ISSUE SUMMARY
Feature
F
OSC
/2
Offset
INL (12-bit mode)
F
RC
Offset
Low-Power mode
Typical Offset
Performance
mode
Endurance
Item
Number
1.1
1.2
1.3
1.4
2.1
3.1
3.2
Issue Summary
F
OSC
/2 not functional.
Time between conversions affects
offset.
INL is ±4 LSb.
ADC not functional if using F
RC
with
F
OSC
<2 MHz.
Offset increases when Common
mode <200 mV.
Improper Low-Power mode
operation.
Normal Speed mode.
Affected Revisions
(1)
B2
X
X
X
X
X
X
X
X
B4
Data EEPROM
4.1
5.1
6.1
6.2
7.1
8.1
9.1
Limited to 10k cycles, V
DD
<2.3V,
PIC16LF1782/1783.
Clock switching can cause a single
corrupted instruction.
Period and falling edge race
condition.
Failure to auto-restart after shutdown
from comparator.
Unexpected Resets may occur at
ambient temperatures below 0
C.
Use of FVR module can cause
device to Reset.
PFM self-write will not work
depending on clock selection.
X
X
X
X
X
X
X
X
X
X
HF Internal Oscillator
Clock Switching
PSMC
PSMC
Low-Dropout (LDO)
Voltage Regulator
FVR
PFM
Note 1:
Rising Edge Input
Auto-shutdown
Low-Power Sleep
FVR Module
PFM Self-Write
Only those issues indicated in the last column apply to the current silicon revision.
DS80000541D-page 2
2012-2014 Microchip Technology Inc.
PIC16(L)F1782/1783
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B4).
1. Module: ADC
1.1 Operation with FOSC/2
The ADC is not functional when the ADCS<2:0>
bits of ADCON1 select the F
OSC
/2 frequency.
Work around
Use the F
RC
selection which provides a valid T
AD
time, regardless of the system clock frequency.
Affected Silicon Revisions
B2
X
1.2 ADC Offset
The offset error exceeds the data sheet
specification when the time between conversions
is greater than 100 us.
Work around
The time dependent error is insignificant when the
time between conversions is less than 100 us.
When the time between conversions is greater
than 100 us, take two back-to-back ADC
conversions and discard the results of the first
conversion.
Affected Silicon Revisions
B2
X
B4
B4
2012-2014 Microchip Technology Inc.
DS80000541D-page 3
PIC16(L)F1782/1783
1.3 ADC INL (12-bit mode)
The ADC linearity is ±4 LSb for the 12-bit mode.
Below are typical INL graphs in 12-bit mode (See
Figure 1
and
Figure 2).
Work around
None.
Affected Silicon Revisions
B2
X
B4
FIGURE 1:
0.5
0.0
-0.5
INL (LSB)
-1.0
-1.5
-2.0
-2.5
-3.0
0
ADC 12-BIT MODE, SINGLE-ENDED INL, V
DD
= 3.0V, T
AD
= 4 us, 25°C,
TYPICAL MEASURED VALUES
512
1024
1536
2048
2560
3072
3584
4096
Output Code
FIGURE 2:
0.5
0.0
-0.5
-1.0
INL (LSB)
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
0
ADC 12-BIT MODE, SINGLE-ENDED INL, V
DD
= 5.5V, T
AD
= 4 us, 25°C,
TYPICAL MEASURED VALUES
512
1024
1536
2048
2560
3072
3584
4096
Output Code
DS80000541D-page 4
2012-2014 Microchip Technology Inc.
PIC16(L)F1782/1783
1.4 Incorrect Readings if using F
OSC
<2 MHz
The ADC is not functional if using F
RC
with F
OSC
frequencies less than 2 MHz.
Work around
Use frequencies greater than 2 MHz for correct
ADC functionality.
Affected Silicon Revisions
B2
X
B4
2. Module: Op Amp
2.1 Offset at Low Common Mode
The op amp offset at Common mode input
voltages below 200 mV increases with respect to
temperature. Below are typical graphs showing
the increase in offset (See
Figure 3, Figure 4
and
Figure 5).
Work around
None.
Affected Silicon Revisions
B2
X
B4
FIGURE 3:
OP AMP TYPICAL OFFSET VOLTAGE AT 25°C,
HIGH GBWP MODE (OPAxSP =
1),
V
DD
= 3.6V, 0V
CMV 5.5V
20
15
Offset Voltage (mV)
10
5
0
-5
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
C
OMMON
M
ODE
V
OLTAGE
(V)
2012-2014 Microchip Technology Inc.
DS80000541D-page 5
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