EFM32 Leopard Gecko
EFM32LG Errata
This document contains information on the errata of EFM32LG. The latest available revision of this device is revision E.
For errata on older revisions, please refer to the errata history section for the device. The device revision is typically the first letter on
the line immediately under the part number on the package marking. This is typically the second or third line.
Errata effective date: April 10th, 2017.
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Rev. 1.20
EFM32LG Errata
Active Errata Summary
1. Active Errata Summary
These tables lists all known errata for the EFM32LG and all unresolved errata in revision E of the EFM32LG.
Table 1.1. Errata History Overview
Designator
Title/Problem
B
ADC_E116
ADC_E117
AES_E101
AES_E102
BU_E101
BU_E102
BU_E104
BU_E105
BU_E106
BURTC_E101
BURTC_E102
CMU_E108
CMU_E110
CMU_E111
CMU_E112
CMU_E113
CMU_E114
CUR_E103
CUR_E104
CUR_E105
DAC_E109
DI_E101
DMA_E101
EBI_E101
EBI_E102
EBI_E103
EMU_E105
EMU_E107
EMU_E110
ETM_E101
Offset in ADC Temperature Sensor Calibration Data
TIMEBASE not wide enough
BYTEORDER Does Not Work in Combination with DATA-
START/XORSTART
AES_STATUS_RUNNING Set One Cycle Late With BYTEOR-
DER Set
Backup Power Increased Power Consumtion
EM4 GPIO Retention in Backup Mode
EM4 with Backup BODs
LFXO Missing Cycles During IOVDD Ramping
Current Leakage in Backup Mode
BURTC LPMODE Entry
BURTC_CNT Read Error
LFxCLKEN Write
LFXO Phase Shift
LFXO Configuration Incorrect
LFXO Boost Buffer Current Setting
LFXO Startup at High Temperature
Device Not Waking Up From EM2 When Using Prescaled Non-
HFRCO Oscillator as HFCLK
Increased EM2 Current
Increased Current on AVDD2 (USB)
Increased Current on AVDD2 (No USB)
DAC Output Drift Over Lifetime
Flash Page Size
EM2 with WFE and DMA
EBI Masking Functionality
EBI Access Fails
Page Mode Read in D16A16ALE Mode
Debug Unavailable During DMA Processing from EM2
Interrupts During EM2 Entry
Potential Hard Fault when Exiting EM2
ETM Trace Clock
—
X
X
X
X
X
X
X
—
X
X
X
X
X
—
—
X
—
X
X
X
X
X
X
X
X
X
X
—
X
Exists on Revision:
C
—
X
X
X
—
—
—
X
—
X
X
—
—
X
—
—
X
X
X
X
X
X
X
—
—
X
—
X
—
—
D
X
X
X
X
—
—
—
X
X
X
X
—
—
—
X
X
X
—
—
—
X
X
X
—
—
X
—
X
—
—
E
—
—
—
—
—
—
—
X
—
—
—
—
—
—
—
—
X
—
—
—
X
—
—
—
—
—
—
X
X
—
Rev. 1.20 | 1
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EFM32LG Errata
Active Errata Summary
Designator
Title/Problem
B
GPIO_E101
LES_E101
LES_E102
LES_E103
OPA_E101
PCNT_E102
PRS_E101
RMU_E101
TIMER_E103
USART_E112
USB_E101
USB_E102
USB_E103
USB_E104
USB_E105
USB_E106
USB_E107
USB_E108
USB_E109
USB_E110
GPIO Wakeup from EM4
LESENSE and Schmitt Trigger
LESENSE and DAC CH1 Configuration
AUXHFRCO and LESENSE
OPAMP 2 Startup Rampup
PCNT Pulse Width Filtering Does Not Work
Edge Detect on GPIO/ACMP
POR Calibration Initialization Issue
Capture/Compare Output is Unreliable with RSSCOIST Ena-
bled
USART AUTOTX Continues to Transmit Even With Full RX
Buffer
USB DMA Transfers with Prescaled HFCLK
USB Datalines
HNP Sequence Fails if A-Device Connects After 3.4 ms
USB A-Device Delays the HNP Switch Back Process
B-Device as Host Driving K-J Pairs During Reset
USB Interrupts
Entry to EM4 Causes Temporary Leakage from VREGO
Floating DM/DP Pins Cause Leakage when USB is Disabled
Missing USB_GINTSTS.SESSREQINT Interrupt with
USB_PCGCCTL.STOPPCLK = 1
Unexpected USB_HCx_INT.CHHLTD Interrupt
X
X
X
—
X
X
X
—
X
X
X
X
X
X
X
X
X
X
X
X
Exists on Revision:
C
—
—
—
—
—
X
X
—
X
X
—
—
X
X
X
—
X
X
X
X
D
—
—
—
X
—
X
X
—
X
X
—
—
X
X
X
—
—
—
X
X
E
—
—
—
—
—
X
—
X
X
—
—
—
X
X
X
—
—
—
X
X
Table 1.2. Active Errata Status Summary
Errata #
Designator
Title/Problem
Workaround
Exists
1
2
3
4
5
6
BU_E105
CMU_E114
DAC_E109
EMU_E107
EMU_E110
PCNT_E102
LFXO Missing Cycles During IOVDD Ramping
Device Not Waking Up From EM2 When Using Pre-
scaled Non-HFRCO Oscillator as HFCLK
DAC Output Drift Over Lifetime
Interrupts During EM2 Entry
Potential Hard Fault when Exiting EM2
PCNT Pulse Width Filtering Does Not Work
Yes
Yes
Yes
Yes
Yes
No
Affected
Revision
E
E
E
E
E
E
—
—
—
—
E, targeted for Q4
2017
—
Resolution
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Rev. 1.20 | 2
EFM32LG Errata
Active Errata Summary
Errata #
Designator
Title/Problem
Workaround
Exists
7
RMU_E101
POR Calibration Initialization Issue
Yes
Affected
Revision
E
E devices (date
code ≥ 1539 and
PROD_REV ≥
0x96)
—
—
—
—
—
—
Resolution
8
9
10
11
12
13
TIMER_E103
USB_E103
USB_E104
USB_E105
USB_E109
USB_E110
Capture/Compare Output is Unreliable with RSSCO-
IST Enabled
HNP Sequence Fails if A-Device Connects After 3.4
ms
USB A-Device Delays the HNP Switch Back Process
B-Device as Host Driving K-J Pairs During Reset
Missing USB_GINTSTS.SESSREQINT Interrupt with
USB_PCGCCTL.STOPPCLK = 1
Unexpected USB_HCx_INT.CHHLTD Interrupt
No
No
No
No
Yes
Yes
E
E
E
E
E
E
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Rev. 1.20 | 3
EFM32LG Errata
Detailed Errata Descriptions
2. Detailed Errata Descriptions
2.1 BU_E105 — LFXO Missing Cycles During IOVDD Ramping
Description of Errata
LFXO missing cycles during IOVDD ramping when used in combination with Backup mode.
Affected Conditions / Impacts
When IOVDD is ramped, the dc-level of the XTAL signal changes, resulting in missed LFXO cycles and possible glitches on the LFXO
clock.
Workaround
Set PRESC in BURTC_CTRL to greater then 0 when ramping IOVDD in combination with Backup mode to avoid glitches on the
LFXO clock.
Resolution
There is currently no resolution for this issue.
2.2 CMU_E114 — Device Not Waking Up From EM2 When Using Prescaled Non-HFRCO Oscillator as HFCLK
Description of Errata
Device not waking up from EM2 when using prescaled non-HFRCO oscillator as HFCLK.
Affected Conditions / Impacts
If the device is running from any prescaled oscillator other than HFRCO as HFCLK and HFRCO is disabled, the device will not wake
up from EM2.
Workaround
Before entering EM2, clear CMU_CTRL_HFCLKDIV. Alternatively, enable HFRCO by setting CMU_OSCENCMD_HFRCOEN and
wait until CMU_STATUS_HFRCORDY is set.
Resolution
There is currently no resolution for this issue.
2.3 DAC_E109 — DAC Output Drift Over Lifetime
Description of Errata
The voltage output of the DAC might drift over time.
Affected Conditions / Impacts
When the device is powered and the DAC is disabled, stress on an internal circuit node can cause the output voltage of the DAC to
drift over time, and in some cases may violate the V
DACOFFSET
specification. If the DAC is always enabled while the device is pow-
ered, this condition cannot occur.
Workaround
Both in the startup initialization code and prior to disabling the DAC in application code, set the OPAnSHORT bit in DACn_OPACTRL
to a '1' for the corresponding DAC(s) used by the application. This will prevent the output voltage drift over time effect.
Resolution
There is currently no resolution for this issue.
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Rev. 1.20 | 4
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