Features
•
8-bit Microcontroller Compatible with 8051 Products
•
Enhanced 8051 Architecture
Single Clock Cycle per Byte Fetch
12 Clock per Machine Cycle Compatibility Mode
Up to 20 MIPS Throughput at 20 MHz Clock Frequency
Fully Static Operation: 0 Hz to 20 MHz
On-chip 2-cycle Hardware Multiplier
16x16 Multiply–Accumulate Unit
256 x 8 Internal RAM
On-chip 2KB Expanded RAM (ERAM)
• Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048 Bytes)
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 64KB of In-System Programmable (ISP) Flash Program Memory
– 4KB of EEPROM (AT89LP51ED2/ID2 Only)
– 512-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Bootloader
Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Seven 8-bit PWM Outputs
– 16-bit Programmable Counter Array
• High Speed Output, Compare/Capture
• Pulse Width Modulation, Watchdog Timer Capabilities
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
–
Two Wire Interface 400K bit/s
– Programmable Watchdog Timer with Software Reset
– 8 General-purpose Interrupt and Keyboard Interface Pins
Special Microcontroller Features
– Dual Oscillator Support: Crystal, 32 kHz Crystal, 8 MHz Internal (AT89LP51ID2)
– Two-wire On-Chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– 8-bit Clock Prescaler
I/O and Packages
– Up to 40 Programmable I/O Lines
– Green (Pb/Halide-free) PLCC44, VQFP44, QFN44. PDIP40
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style), Input-only (Tristate)
• Push-pull CMOS Output, Open-drain
Operating Conditions
– 2.4V to 5.5V V
CC
Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V (Single-cycle)
–
–
–
–
–
–
–
–
•
8-bit Flash
Microcontroller
with 64K bytes
Program
Memory
AT89LP51RD2
AT89LP51ED2
AT89LP51ID2
Preliminary
•
•
•
•
3714A–MICRO–7/11
1. Pin Configurations
1.1
44-lead TQFP/LQFP
P1.4 (CEX1/SS†)
P1.3 (CEX0)
P1.2 (ECI)
P1.1 (T2 EX/SS)
P1.0 (T2/XTAL1B‡)
P4.2 (XTAL2B‡)
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
44
43
42
41
40
39
38
37
36
35
34
(†MOSI/CEX2/MISO) P1.5
(†MISO/CEX3/SCK) P1.6
(†SCK/CEX4/MOSI) P1.7
(DCL) RST
(RXD) P3.0
(SDA) P4.1
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
POL
P4.0 (SCL)
P4.4 (ALE)
P4.5 (PSEN)
P2.7 (A15/AIN3)
P2.6 (A14/AIN2)
P2.5 (A13/AIN1)
1.2
44-lead PLCC
P1.4 (CEX1/SS†)
P1.3 (CEX0)
P1.2 (ECI)
P1.1 (T2 EX/SS)
P1.0 (T2/XTAL1B‡)
P4.2 (XTAL2B‡)
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
2
AT89LP51RD2/ED2/ID2 Preliminary
3714A–MICRO–7/11
(WR) P3.6
(RD) P3.7
(XTAL2A) P4.7
(XTAL1A) P4.6
VSS
(DDA) P4.3
(A8) P2.0
(A9) P2.1
(DAC-/A10) P2.2
(DAC+/A11) P2.3
(AIN0/A12) P2.4
† SPI in remap mode
‡ AT89LP51ID2 Only
18
19
20
21
22
23
24
25
26
27
28
(†MOSI/CEX2/MISO) P1.5
(†MISO/CEX3/SCK) P1.6
(†SCK/CEX4/MOSI) P1.7
(DCL) RST
(RXD) P3.0
(SDA) P4.1
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
(WR) P3.6
(RD) P3.7
(XTAL2A) P4.7
(XTAL1A) P4.6
VSS
(DDA) P4.3
(A8) P2.0
(A9) P2.1
(DAC-/A10) P2.2
(DAC+/A11) P2.3
(AIN0/A12) P2.4
† SPI in remap mode
‡ AT89LP51ID2 Only
39
38
37
36
35
34
33
32
31
30
29
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
POL
P4.0 (SCL)
P4.4 (ALE)
P4.5 (PSEN)
P2.7 (A15/AIN3)
P2.6 (A14/AIN2)
P2.5 (A13/AIN1)
AT89LP51RD2/ED2/ID2 Preliminary
1.3
44-pad VQFN/QFN/MLF
P1.4 (CEX1/SS†)
P1.3 (CEX0)
P1.2 (ECI)
P1.1 (T2 EX/SS)
P1.0 (T2/XTAL1B‡)
P4.2 (XTAL2B‡)
VDD
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
44
43
42
41
40
39
38
37
36
35
34
† SPI in remap mode
‡ AT89LP51ID2 Only
(†MOSI/CEX2/MISO) P1.5
(†MISO/CEX3/SCK) P1.6
(†SCK/CEX4/MOSI) P1.7
(DCL) RST
(RXD) P3.0
(SDA) P4.1
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
POL
P4.0 (SCL)
P4.4 (ALE)
P4.5 (PSEN)
P2.7 (A15/AIN3)
P2.6 (A14/AIN2)
P2.5 (A13/AIN1)
1.4
40-pin PDIP
(T2) P1.0
(SS/T2EX) P1.1
(ECI) P1.2
(CEX0) P1.3
(†SS/CEX1) P1.4
(†MOSI/CEX2/MISO) P1.5
(†MISO/CEX3/SCL) P1.6
(†SCK/CEX4/MOSI) P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
(XTAL2A) P4.7
(XTAL1A) P4.6
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
POL
P4.4 (ALE)
P4.5 (PSEN)
P2.7 (A15/AIN3)
P2.6 (A14/AIN2)
P2.5 (A13/AIN1)
P2.4 (A12/AIN0)
P2.3 (A11/DAC+)
P2.2 (A10/DAC-)
P2.1 (A9)
P2.0 (A8)
Note:
1. The AT89LP51ID2 is not
available
in the PDIP package
(WR) P3.6
(RD) P3.7
(XTAL2A) P4.7
(XTAL1A) P4.6
GND
(DDA) P4.3
(A8) P2.0
(A9) P2.1
(DA-/A10) P2.2
(DA+/A11) P2.3
(AIN0/A12) P2.4
NOTE:
Bottom pad
should be
soldered
to ground
†SPI in remap mode
3
3714A–MICRO–7/11
1.5
Pin Description
Atmel AT89LP51RD2/ED2/ID2 Pin Description
(1)
Table 1-1.
VQFP
VQFN
Pin Number
PLCC
PDIP
Symbol
Type
I/O
I/O
1
7
6
P1.5
I/O
Description
P1.5:
User-configurable I/O Port 1 bit 5.
MISO:
SPI
master-in/slave-out. When configured
as
master, this pin is
an
input. When
configured
as
slave, this pin is
an
output.
MOSI:
SPI
master-out/slave-in (Remap mode). When configured
as
master, this pin is
an
output.
When configured
as
slave, this pin is
an
input. During In-System Programming, this pin is
an
input.
CEX2:
Capture/Compare external I/O for PCA module 2.
P1.6:
User-configurable I/O Port 1 bit 6.
SCK:
SPI
Clock. When configured
as
master, this pin is
an
output. When configured
as
slave,
this pin is
an
input.
MISO:
SPI
master-in/slave-out (Remap mode). When configured
as
master, this pin is
an
input.
When configured
as
slave, this pin is
an
output. During In-System Programming, this pin is
an
output.
CEX3:
Capture/Compare external I/O for PCA module 3.
P1.7:
User-configurable I/O Port 1 bit 7.
MOSI:
SPI
master-out/slave-in. When configured
as
master, this pin is
an
output. When
configured
as
slave, this pin is
an
input.
SCK:
SPI
Clock (Remap mode). When configured
as
master, this pin is
an
output. When
configured
as
slave, this pin is
an
input. During In-System Programming, this pin is
an
input.
CEX4:
Capture/Compare external I/O for PCA module 4.
RST:
External Reset input (Reset polarity depends on POL pin.
See
“External Reset” on page
55.).
The RST pin can output
a
pulse when the internal Watchdog reset or POR is
active.
DCL:
Serial
Debug Clock input for On-Chip Debug Interface when OCD is enabled.
P3.0:
User-configurable I/O Port 3 bit 0.
RXD:
Serial
Port Receiver Input.
P4.1:
User-configurable I/O Port 4bit 1.
SDA:
TWI bidirectional
Serial
Data line.
P3.1:
User-configurable I/O Port 3 bit 1.
TXD:
Serial
Port Transmitter Output.
P3.2:
User-configurable I/O Port 3 bit 2.
INT0:
External Interrupt 0 Input or Timer 0 Gate Input.
P3.3:
User-configurable I/O Port 3 bit 3.
INT1:
External Interrupt 1 Input or Timer 1 Gate Input
P3.4:
User-configurable I/O Port 3 bit 4.
T1:
Timer/Counter 0 External input or output.
P3.5:
User-configurable I/O Port 3 bit 5.
T1:
Timer/Counter 1 External input or output.
P3.6:
User-configurable I/O Port 3 bit 6.
WR:
External memory interface Write
Strobe
(active-low).
P3.7:
User-configurable I/O Port 3 bit 7.
RD:
External memory interface Read
Strobe
(active-low).
P4.7:
User-configurable I/O Port 4 bit 7.
XTAL2A:
Output from inverting oscillator
amplifier
A. It may be
used as a
port pin if the internal
RC oscillator or external clock is selected
as
the clock source A.
P4.6:
User-configurable I/O Port 4 bit 6.
XTAL1A:
Input to the inverting oscillator
amplifier
A
and
internal clock generation circuits. It may
be
used as a
port pin if the internal RC oscillator is selected
as
the clock source A.
I/O
I/O
I/O
2
8
7
P1.6
I/O
I/O
I/O
I/O
3
9
8
P1.7
I/O
I/O
I/O
4
10
9
RST
I
5
6
7
8
9
10
11
12
13
14
15
16
11
12
13
14
10
P3.0
P4.1
P3.1
P3.2
P3.3
P3.4
I/O
I
I/O
I/O
I/O
O
I/O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
O
I/O
I
11
17
15
P3.5
12
18
16
P3.6
13
19
17
P3.7
14
20
18
P4.7
15
21
19
P4.6
4
AT89LP51RD2/ED2/ID2 Preliminary
3714A–MICRO–7/11
AT89LP51RD2/ED2/ID2 Preliminary
Table 1-1.
VQFP
VQFN
16
17
18
19
Atmel AT89LP51RD2/ED2/ID2 Pin Description
(1)
Pin Number
PLCC
22
23
24
25
21
22
PDIP
20
Symbol
GND
P4.3
P2.0
P2.1
Type
I
I/O
I/O
I/O
O
I/O
O
I/O
O
O
I/O
O
O
I/O
I
O
I/O
I
O
I/O
I
O
I/O
I
O
I/O
O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
I/O
I
Description
Ground
P4.3:
User-configurable I/O Port 4bit 3.
DDA:
Bidirectional Debug Data line for the On-Chip Debug Interface when OCD is enabled.
P2.0:
User-configurable I/O Port 2 bit 0.
A8:
External memory interface Address bit
8.
P2.1:
User-configurable I/O Port 2 bit 1.
A9:
External memory interface Address bit 9.
P2.2:
User-configurable I/O Port 2 bit 2.
DA-:
DAC negative differential output.
A10:
External memory interface Address bit 10.
P2.3:
User-configurable I/O Port 2 bit 3.
DA+-:
DAC positive differential output.
A11:
External memory interface Address bit 11.
P2.4:
User-configurable I/O Port 2 bit 5.
AIN0:
Analog Comparator Input 0.
A12:
External memory interface Address bit 12.
P2.5:
User-configurable I/O Port 2 bit 5.
AIN1:
Analog Comparator Input 1.
A13:
External memory interface Address bit 13.
P2.6:
User-configurable I/O Port 2 bit 6.
AIN2:
Analog Comparator Input 2.
A14:
External memory interface Address bit 14.
P2.7:
User-configurable I/O Port 2 bit 7.
AIN3:
Analog Comparator Input 3.
A15:
External memory interface Address bit 15.
P4.5:
User-configurable I/O Port 4 bit 5.
PSEN:
External memory interface Program
Store
Enable (active-low).
P4.4:
User-configurable I/O Port 4 bit 4.
ALE:
External memory interface Address Latch Enable.
P4.0:
User-configurable I/O Port 4 bit 0.
SCL:
TWI
Serial
Clock line. This line is
an
output in mater mode
and an
input in slave mode.
POL:
Reset polarity (See
“External Reset” on page 55.)
P0.7:
User-configurable I/O Port 0 bit 7.
AD7:
External memory interface Address/Data bit 7.
P0.6:
User-configurable I/O Port 0 bit 6.
AD6:
External memory interface Address/Data bit 6.
ADC6:
ADC
analog
input 6.
P0.5:
User-configurable I/O Port 0 bit 5.
AD5:
External memory interface Address/Data bit 5.
ADC5:
ADC
analog
input 5.
P0.4:
User-configurable I/O Port 0 bit 4.
AD4:
External memory interface Address/Data bit 4.
ADC4:
ADC
analog
input 4.
P0.3:
User-configurable I/O Port 0 bit 3.
AD3:
External memory interface Address/Data bit 3.
ADC3:
ADC
analog
input 3.
20
26
23
P2.1
21
27
24
P2.3
22
28
25
P2.4
23
29
26
P2.5
24
30
27
P2.6
25
31
28
P2.7
26
27
28
29
30
32
33
34
35
36
29
30
P4.5
P4.4
P4.0
31
32
POL
P0.7
31
37
33
P0.6
32
38
34
P0.5
33
39
35
P0.4
34
40
36
P0.3
5
3714A–MICRO–7/11
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