PIC24F16KL402 FAMILY
PIC24F16KL402 Family
Silicon Errata and Data Sheet Clarification
The PIC24F16KL402 family devices that you have
received conform functionally to the current Device
Data Sheet (DS30001037C), except for the anomalies
described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC24F16KL402 family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the issues
indicated in the last column of
Table 2
apply to the current silicon revision (A2).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1.
Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
From the main menu in MPLAB IDE, select
Configure>Select Device,
and then select the
target part number in the dialog box.
Select
the
MPLAB
hardware
tool
(Debugger>Select
Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number
and
Device
Revision ID value appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
2.
3.
4.
Data Sheet clarifications and corrections start on
Page 4,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s pro-
grammers, debuggers, and emulation tools, which are
available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC24F16KL402
family silicon revisions are shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Device ID
(1)
Revision ID for
Silicon Revision
(2)
A0
A1
A2
PIC24F08KL302
PIC24F08KL401
0000h 0001h 0002h PIC24F08KL402
PIC24F16KL401
PIC24F16KL402
4B00h
4B0Eh
4B04h
4B1Eh
4B14h
0000h 0001h 0002h
Part Number
Device ID
(1)
Revision ID for
Silicon Revision
(2)
A0
A1
A2
Part Number
PIC24F04KL100
PIC24F04KL101
PIC24F08KL200
PIC24F08KL201
PIC24F08KL301
Note 1:
2:
4B01h
4B02h
4B05h
4B06h
4B0Ah
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the
“PIC24FXXKMXXX/KLXXX Flash Programming Specifications”
(DS30625) for detailed
information on Device and Revision IDs for your specific device.
2011-2016 Microchip Technology Inc.
DS80000534E-page 1
PIC24F16KL402 FAMILY
TABLE 2:
Module
SILICON ISSUE SUMMARY
Feature
Item
Number
1.
2.
3.
Issue Summary
Affected
Revisions
(1)
A0
A1
A2
UART (Transmit)
HLVD (Band Gap
Reference)
Note 1:
Transmit
Band Gap
Reference
UTXBF flag may not indicate correctly.
REFO output unavailable at higher frequencies.
BGVST and IRVST bits may not become set at
extremely low temperatures.
X
X
X
X
X
X
X
Oscillator (REFO)
REFO
Only those issues indicated in the last column apply to the current silicon revision.
DS80000534E-page 2
2011-2016 Microchip Technology Inc.
PIC24F16KL402 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
2. Module: Oscillator (REFO)
When output frequencies above 16 MHz are
selected for the Reference Clock Output
(REFO), the peak output voltage on the REFO
pin may be too low to be properly detected by
external devices.
Work around
None.
Affected Silicon Revisions
A0
X
A1
X
A2
X
1. Module: UART (Transmit)
The Transmit Buffer Full Flag, UTXBF
(UxSTA<9>), may become cleared before data
starts moving out of the full buffer. If the flag is
used to determine when data can be written to
the buffer, new data may not be accepted, and
data may not be transmitted.
Work around
Poll the Transmit Buffer Empty Flag, TRMT
(UxSTA<8>), to determine when the transmit
buffer is empty and can be written to.
Alternatively, configure the UART to set the
Transmit Interrupt Flag (UxTXIF) whenever a
character is shifted into the Transmit Shift Reg-
ister (UTXISEL<1:0> =
00).
When a transmit
interrupt occurs, this indicates that at least one
buffer position is open and that the buffer can be
written to.
Affected Silicon Revisions
A0
X
A1
A2
3. Module: HLVD (Band Gap Reference)
At the extreme low end of the operating tem-
perature range (near -40°C), the BGVST and
IRVST flag bits (HLVDCON<6,5>) may not
become set when the voltage references are
stable and ready to use.
Work around
For applications that run at extremely cold tem-
peratures, do not use the BGVST and IRVST
bits as the sole indicator of band gap readiness.
Include a time-out of 750 µs between enabling
and using a reference.
Affected Silicon Revisions
A0
X
A1
X
A2
X
2011-2016 Microchip Technology Inc.
DS80000534E-page 3
PIC24F16KL402 FAMILY
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS30001037C):
Note:
Corrections and additions are shown in
bold.
Where possible, the original bold
text formatting has been removed for
clarity.
2. Module: Special Features
In Register 23-6: FPOR: Reset Configuration
Register, the description for BORV<1:0> has
been updated. The change is shown in
bold
below:
bit 6-5 BORV<1:0>: Brown-out Reset
Voltage
Threshold
bits
(2)
11
= Brown-out Reset is set to the low trip point
10
= Brown-out Reset is set to the middle trip
point
01
= Brown-out Reset is set to the high trip point
00
= Downside protection on POR is enabled
(Low-Power BOR is selected)
1. Module: I/O Ports
The following is appended to the end of
Section 11.2.1 “Analog Selection Register”:
“On devices which do not have an A/D Con-
verter, it is still necessary to configure the ANSx
registers in order to enable digital input buffers.
Any I/O pins with an ANx function listed in red in
the device pinout diagrams (Pages 3 through 5)
will default to have the digital input buffer
disabled.”
3. Module: Pin Diagrams
The Pin Diagram: PIC24FXXKL301/401 20-Pin
PDIP/SSOP/SOIC has the functions reversed
for Pin 6 and Pin 10. The corrected pin functions
are shown in
bold
below.
Pin Diagrams: PIC24FXXKL301/401
20-Pin PDIP/SSOP/SOIC
(1)
MCLR/V
PP
/RA5
PGEC2/V
REF
+/CV
REF
+/AN0/SDA2/SDI2/CN2/RA0
PGED2/CV
REF
-/V
REF
-/AN1/SDO2/CN3/RA1
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
AN4/T3G/U1RX/CN6/RB2
OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2
OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3
PGED3/SOSCI/AN15/U2RTS/CN1/RB4
PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
V
SS
AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15
CV
REF
/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14
AN11/SDO1/P1D/CN13/RB13
AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12
C2OUT/CCP1/P1A/INT2/CN8/RA6
SDA1/T1CK/U1RTS/CCP3/CN21/RB9
SCL1/U1CTS/SS1/CN22/RB8
U1TX/INT0/CN23/RB7
PIC24FXXKL301
(2)
PIC24FXXKL401
DS80000534E-page 4
2011-2016 Microchip Technology Inc.
PIC24F16KL402 FAMILY
APPENDIX A:
DOCUMENT
REVISION HISTORY
Rev A Document (11/2011)
Initial release of this document; issued for revision A0.
Includes silicon issues 1 (UART, Transmit) and
2 (Oscillator, REFO).
Rev B Document (4/2012)
Adds silicon issue 3 (HLVD, Band Gap Reference) to
revision A0.
Adds data sheet clarifications 1 (Front Matter, Device
Features), 2 (Pin Diagrams), 3 (Overview), 4 (I/O
Ports), 5 (Master Synchronous Serial Port – MSSP)
and 6 (Comparator).
Rev C Document (4/2013)
Adds silicon revision A1.
Rev D Document (3/2014)
Removes data sheet clarifications that were addressed
in current Device Data Sheet (DS30001037C).
Adds data sheet clarifications 2 (Special Features) and
3 (Pin Diagrams).
Rev E Document (1/2016)
Adds silicon revision A2.
2011-2016 Microchip Technology Inc.
DS80000534E-page 5
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